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W7500P
Wiznet W7500P Manuals
Manuals and User Guides for Wiznet W7500P. We have
2
Wiznet W7500P manuals available for free PDF download: Reference Manual, Information
Wiznet W7500P Reference Manual (399 pages)
W7500 Series
Brand:
Wiznet
| Category:
Controller
| Size: 13.31 MB
Table of Contents
1 Table of Contents
2
2 List of Table
19
3 List of Figures
21
4 Documentation Conventions
23
Glossary
23
Register Bit Conventions
25
5 System and Memory Overview
26
System Architecture
26
Memory Organization
27
Introduction
27
Memory Map
28
6 System Configuration Controller (SYSCFG)
29
7 Interrupt and Events
29
Nested Vectored Interrupt Controller (NVIC)
29
NVIC Main Features
29
Systick Calibration Value Register
29
Interrupt and Exception Vectors
29
Event
30
8 Power Supply
31
Introduction
31
Voltage Regulator
31
Low-Power Modes
31
Sleep Mode
32
Peripheral Clock Gating
32
9 System Tick Timer
33
Introduction
33
Features
33
Functional Description
33
Registers (Base : 0Xe000_E000)
34
System Timer Control and Status Register (SYST_CSR)
34
Systick Reload Value Register (SYST_RVR)
34
Systick Current Value Register (SYST_CVR)
35
Systick Calibration Value Register (SYST_CALIB)
35
10 Booting Sequence
36
11 Embedded Flash Memory
37
Flash Main Features
37
Flash Memory Organization
37
12 Clock Reset Generator (CRG)
39
Introduction
39
Features
39
Reset
39
Clock
40
Functional Description
41
External Oscillator Clock
41
RC Oscillator Clock
42
Pll
42
Generated Clock
42
Registers (Base Address : 0X4100_1000)
44
OSC Power down Register (OSC_PDR)
44
PLL Power down Register (PLL_PDR)
44
PLL Frequency Calculating Register (PLL_FCR)
44
PLL Output Enable Register (PLL_OER)
45
PLL Bypass Register (PLL_BPR)
45
PLL Input Clock Source Select Register (PLL_IFSR)
46
FCLK Source Select Register (FCLK_SSR)
46
FCLK Prescale Value Select Register (FCLK_PVSR)
47
SSPCLK Source Select Register (SSPCLK_SSR)
47
SSPCLK Prescale Value Select Register (SSPCLK_PVSR)
48
ADCCLK Source Select Register (ADCCLK_SSR)
48
ADCCLK Prescale Value Select Register (ADCCLK_PVSR)
48
TIMER0CLK Source Select Register (TIMER0CLK_SSR)
49
TIMER0CLK Prescale Value Select Register (TIMER0CLK_PVSR)
49
TIMER1CLK Source Select Register (TIMER1CLK_SSR)
50
TIMER1CLK Prescale Value Select Register (TIMER1CLK_PVSR)
50
PWM0CLK Source Select Register (PWM0CLK_SSR)
51
PWM0CLK Prescale Value Select Register (PWM0CLK_PVSR)
51
PWM1CLK Source Select Register (PWM1CLK_SSR)
52
PWM1CLK Prescale Value Select Register (PWM1CLK_PVSR)
52
PWM2CLK Source Select Register (PWM2CLK_SSR)
53
PWM2CLK Prescale Value Select Register (PWM2CLK_PVSR)
53
PWM3CLK Source Select Register (PWM3CLK_SSR)
54
PWM3CLK Prescale Value Select Register (PWM3CLK_PVSR)
55
PWM4CLK Source Select Register (PWM4CLK_SSR)
55
PWM4CLK Prescale Value Select Register (PWM4CLK_PVSR)
56
PWM5CLK Source Select Register (PWM5CLK_SSR)
56
PWM5CLK Prescale Value Select Register (PWM5CLK_PVSR)
57
PWM6CLK Source Select Register (PWM6CLK_SSR)
57
PWM6CLK Prescale Value Select Register (PWM6CLK_PVSR)
58
PWM7CLK Source Select Register (PWM7CLK_SSR)
58
PWM7CLK Prescale Value Select Register (PWM7CLK_PVSR)
59
RTC High Speed Source Select Register (RTC_HS_SSR)
59
RTC High Speed Prescale Value Select Register (RTC_HS_PVSR)
60
RTC Source Select Register (RTC_SSR)
60
WDOGCLK High Speed Source Select Register (WDOGCLK_HS_SSR)
61
WDOGCLK High Speed Prescale Value Select Register (WDOGCLK_HS_PVSR)
61
WDOGCLK Clock Source Select Register (WDOGCLK_SSR)
62
UARTCLK Source Select Register (UARTCLK_SSR)
62
UARTCLK Prescale Value Select Register (UARTCLK_PVSR)
63
MIICLK Enable Control Register (MIICLK_ECR)
63
Monitoring Clock Source Select Register (MONCLK_SSR)
64
Register Map
65
13 Tcp/Ip Core Offload Engine (TOE)
67
Introduction
67
Features
67
Functional Description
68
TOE Memory Map
68
Common Register Map
70
Socket Register Map
70
Memory
71
Common Register (Base : 0X4600_0000)
73
VERSIONR (TOE Version Register)
73
TCKCNTR (Ticker Counter Register)
73
IR (Interrupt Register)
74
IMR (Interrupt Mask Register)
74
IRCR (Interrupt Clear Register)
75
SIR (Socket Interrupt Register)
76
SIMR (Socket Interrupt Mask Register)
76
MR (Mode Register)
77
PTIMER (PPP Link Control Protocol Request Timer Register)
78
PMAGICR (PPP Link Control Protocol Magic Number Register)
78
PHAR (Destination Hardware Address Register in Pppoe)
78
PSIDR (Session ID Register in Pppoe)
79
PMRUR (Maximum Receive Unit Register in Pppoe)
80
SHAR (Source Hardware Address Register)
80
GAR (Gateway Address)
81
SUBR ( Subnet Mask Register)
81
SIPR (Source IP Address Register)
82
NCONFLR ( Network Configuration Lock Register)
82
RTR (Retry Time Register)
83
RCR (Retry Counter Register)
84
UIPR (Unreachable IP Address Register)
85
UPORTR (Unreachable Port Register)
86
Socket Register (Base : 0X4601_0000 + 0X0004_000 X N)[N=0
86
Sn_Mr (Socket N Mode Register)
86
Sn_Cr (Socket N Command Register)
89
Sn_Ir (Socket N Interrupt Register)
91
Sn_Imr (Socket N Interrupt Mask Register)
91
Sn_Icr (Socket N Interrupt Clear Register)
92
Sn_Sr (Socket N Status Register)
93
Sn_Pnr (Socket N Protocol Number Register)
95
Sn_Tosr (Socket N IP Type of Service Register)
96
Sn_Ttlr (Socket N TTL Register)
96
Sn_Fragr (Socket N Fragment Offset Register)
97
Sn_Mssr (Socket N Maximum Segment Register)
97
Sn_Portr (Socket N Source Port Register)
98
Sn_Dhar (Socket N Destination Hardware Address Register)
98
Sn_Dportr (Socket N Destination Port Number Register)
99
Sn_Dipr (Socket N Destination IP Address Register)
100
Sn_Katmr (Socket N Keep Alive Timer Register)
101
Sn_Rtr (Socket N Retry Time Register)
101
Sn_Rcr (Socket N Retry Counter Register)
102
Sn_Txbuf_Size (Socket N TX Buffer Size Register)
102
Sn_Tx_Fsr (Socket N TX Free Size Register)
103
Sn_Tx_Rd (Socket N TX Read Pointer Register)
104
Sn_Tx_Wr (Socket N TX Write Pointer Register)
105
Sn_Rxbuf_Size (Socket N RX Buffer Size Register)
105
Sn_Rx_Rsr (Socket N RX Received Size Register)
106
Sn_Rx_Rd (Socket N RX Read Pointer Register)
107
Sn_Rx_Wr (Socket N RX Write Pointer Register)
108
14 Random Number Generator (RNG)
109
Introduction
109
Features
109
Functional Description
109
Operation RNG
110
Registers (Base Address : 0X4000_7000)
111
RNG Run Register (RNG_RUN)
111
RNG SEED Register (RNG_SEED)
111
RNG Clock Select Register (RNG_CLKSEL)
111
RNG Manual Mode Select Register (RNG_MODE)
112
RNG Random Number Value Register (RNG_RN)
112
RNG Polynomial Register (RNG_POLY)
113
Register Map
114
15 Alternate Function Controller (AFC)
114
Introduction
114
Features
114
Functional Description
114
Registers (Base Address : 0X4100_2000)
117
PA_00 Pad Alternate Function Select Register (PA_00_AFR)
117
PA_01 Pad Alternate Function Select Register (PA_01_AFR)
117
PA_02 Pad Alternate Function Select Register (PA_02_AFR)
118
PA_03 Pad Alternate Function Select Register (PA_03_AFR)
118
PA_04 Pad Alternate Function Select Register (PA_04_AFR)
119
PA_05 Pad Alternate Function Select Register (PA_05_AFR)
119
PA_06 Pad Alternate Function Select Register (PA_06_AFR)
120
PA_07 Pad Alternate Function Select Register (PA_07_AFR)
120
PA_08 Pad Alternate Function Select Register (PA_08_AFR)
121
PA_09 Pad Alternate Function Select Register (PA_09_AFR)
121
PA_10 Pad Alternate Function Select Register (PA_10_AFR)
122
PA_11 Pad Alternate Function Select Register (PA_11_AFR)
122
PA_12 Pad Alternate Function Select Register (PA_12_AFR)
123
PA_13 Pad Alternate Function Select Register (PA_13_AFR)
123
PA_14 Pad Alternate Function Select Register (PA_14_AFR)
124
PA_15 Pad Alternate Function Select Register (PA_15_AFR)
124
PB_00 Pad Alternate Function Select Register (PB_00_AFR)
125
PB_01 Pad Alternate Function Select Register (PB_01_AFR)
125
PB_02 Pad Alternate Function Select Register (PB_02_AFR)
126
PB_03 Pad Alternate Function Select Register (PB_03_AFR)
126
PB_04 Pad Alternate Function Select Register (PB_04_AFR)
127
PB_05 Pad Alternate Function Select Register (PB_05_AFR)
127
PB_06 Pad Alternate Function Select Register (PB_06_AFR)
128
PB_07 Pad Alternate Function Select Register (PB_07_AFR)
128
PB_08 Pad Alternate Function Select Register (PB_08_AFR)
129
PB_09 Pad Alternate Function Select Register (PB_09_AFR)
129
PB_10 Pad Alternate Function Select Register (PB_10_AFR)
130
PB_11 Pad Alternate Function Select Register (PB_11_AFR)
130
PB_12 Pad Alternate Function Select Register (PB_12_AFR)
131
PB_13 Pad Alternate Function Select Register (PB_13_AFR)
131
PB_14 Pad Alternate Function Select Register (PB_14_AFR)
132
PB_15 Pad Alternate Function Select Register (PB_15_AFR)
132
PC_00 Pad Alternate Function Select Register (PC_00_AFR)
133
PC_01 Pad Alternate Function Select Register (PC_01_AFR)
133
PC_02 Pad Alternate Function Select Register (PC_02_AFR)
134
PC_03 Pad Alternate Function Select Register (PC_03_AFR)
134
PC_04 Pad Alternate Function Select Register (PC_04_AFR)
135
PC_05 Pad Alternate Function Select Register (PC_05_AFR)
135
PC_06 Pad Alternate Function Select Register (PC_06_AFR)
136
PC_07 Pad Alternate Function Select Register (PC_07_AFR)
136
PC_08 Pad Alternate Function Select Register (PC_08_AFR)
137
PC_09 Pad Alternate Function Select Register (PC_09_AFR)
137
PC_10 Pad Alternate Function Select Register (PC_10_AFR)
138
PC_11 Pad Alternate Function Select Register (PC_11_AFR)
138
PC_12 Pad Alternate Function Select Register (PC_12_AFR)
139
PC_13 Pad Alternate Function Select Register (PC_13_AFR)
139
PC_14 Pad Alternate Function Select Register (PC_14_AFR)
140
PC_15 Pad Alternate Function Select Register (PC_15_AFR)
140
PD_00 Pad Alternate Function Select Register (PD_00_AFR)
141
PD_01 Pad Alternate Function Select Register (PD_01_AFR)
141
PD_02 Pad Alternate Function Select Register (PD_02_AFR)
142
PD_03 Pad Alternate Function Select Register (PD_03_AFR)
142
PD_04 Pad Alternate Function Select Register (PD_04_AFR)
143
Register Map
144
16 External Interrupt (EXTI)
147
Introduction
147
Features
147
Functional Description
147
Registers (Base Address : 0X4100_2000)
149
External Interrupt Enable Register (Px_Y EXTINT)
149
Register Map
149
17 Pad Controller (PADCON)
150
Introduction
150
Features
150
Functional Description
150
Registers (Base Address : 0X4100_3000)
152
PAD Control Register (Px_Y PCR)(X=A..D, Y=0..15
152
Register Map
152
18 General-Purpose I/Os(GPIO)
153
Introduction
153
Features
153
Functional Description
153
Masked Access
154
GPIO Registers(Address Base: 0X4200_0000)
156
GPIO Data Register(Gpiox_Data) (X=A..D
156
GPIO Output Latch Register(Gpiox_Dataout) (X=A..D
156
GPIO Enable Set Register(Gpiox_Outenset) (X=A..D
156
GPIO Enable Clear Register(Gpiox_Outenclr) (X=A..D
157
GPIO Interrupt Enable Set Register(Gpiox_ INTENSET) (X=A..D
157
GPIO Interrupt Enable Clear Register(Gpiox_ INTENCLR) (X=A..D
158
GPIO Interrupt Type Set Register(Gpiox_ INTTYPESET) (X=A..D
158
GPIO Interrupt Type Clear Register(Gpiox_ INTTYPECLR) (X=A..D
159
GPIO Interrupt Polarity Set Register(Gpiox_ INTPOLSET) (X=A..D
159
GPIO Interrupt Polarity Clear Register(Gpiox_ INTPOLCLR) (X=A
160
GPIO Interrupt Status/Clear Register(GPIO_ INTSTATUS/INTCLEAR) (X=A
161
GPIO Lower Byte Masked Access Register(Gpiox_ LB_MASKED) (X=A
161
GPIO Upper Byte Masked Access Register(Gpiox_ UB_MASKED) (X=A
162
Register Map
163
19 Direct Memory Access Controller (DMA)
164
Introduction
164
Features
164
Functional Description
164
DMA Request Mapping
165
DMA Arbitration
165
DMA Cycle Types
165
Registers (Base Address : 0X4100_4000)
168
DMA Status Register (DMA_STATUS)
168
DMA Configuration Register (DMA_CFG)
169
DMA Control Data Base Pointer Register (DMA_CTRL_BASE_PTR)
170
DMA Channel Alternate Control Data Base Pointer Register (DMA_ALT_CTRL_BASE_PTR)
170
DMA Channel Wait on Request Status Register (DMA_WAITONREQ_STATUS)
171
DMA Channel Software Request Register (DMA_CHNL_SW_REQUEST)
171
DMA Channel Useburst Set Register (DMA_CHNL_USEBURST_SET)
172
DMA Channel Useburst Clear Register (DMA_CHNL_USEBURST_CLR)
172
DMA Channel Request Mask Set Register (DMA_CHNL_REQ_MASK_SET)
173
DMA Channel Request Mask Clear Register (DMA_CHNL_REQ_MASK_CLR)
174
DMA Channel Enable Set Register (DMA_CHNL_ENABLE_SET)
174
DMA Channel Enable Clear Register (DMA_CHNL_ENABLE_CLR)
175
DMA Channel Primary-Alternate Set Register (DMA_CHNL_PRI_ALT_SET)
175
DMA Channel Primary-Alternate Clear Register (DMA_CHNL_PRI_ALT
176
DMA Channel Priority Set Register (DMA_CHNL_PRIORITY_SET)
176
DMA Channel Priority Clear Register (DMA_CHNL_PRIORITY_CLR)
177
DMA Bus Error Clear Register (DMA_ERR_CLR)
177
Register Map
179
20 Analog-To-Digital Converter (ADC)
180
Introduction
180
Features
180
Functional Description
181
Operation ADC with Non-Interrupt
181
Operation ADC with Interrupt
183
Registers (Base Address : 0X4100_0000)
183
ADC Control Register (ADC_CTR)
183
ADC Channel Select Register (ADC_CHSEL)
184
ADC Start Register (ADC_START)
185
ADC Conversion Data Register (ADC_DATA)
185
ADC Interrupt Register (ADC_INT)
185
ADC Interrupt Clear Register (ADC_INTCLR)
186
Register Map
187
21 Pulse-Width Modulation (PWM)
188
Introduction
188
Features
188
Functional Description
189
Timer/Counter Control
189
Timer/Counter
189
PWM Mode
193
Interrupt
194
Dead Zone Generation
195
Capture Event
196
How to Set the PWM
198
PWM Channel-0 Registers (Base Address : 0X4000_5000)
198
Channel-0 Interrupt Register(PWMCH0IR)
198
Channel-0 Interrupt Enable Register(PWMCH0IER)
199
Channel-0 Interrupt Clear Register(PWMCH0ICR)
200
Channel-0 Timer/Counter Register (PWMCH0TCR)
200
Channel-0 Prescale Counter Register (PWMCH0PCR)
201
Channel-0 Prescale Register (PWMCH0PR)
201
Channel-0 Match Register (PWMCH0MR)
201
Channel-0 Limit Register (PWMCH0LR)
202
Channel-0 Up-Down Mode Register (PWMCH0UDMR)
202
Channel-0 Timer/Counter Mode Register (PWMCH0TCMR)
203
Channel-0 PWM Output Enable and External Input Enable Register (PWMCH0PEEER)
203
Channel-0 Capture Mode Register (PWMCH0CMR)
204
Channel-0 Capture Register (PWMCH0CR)
204
Channel-0 Periodic Mode Register (PWMCH0PDMR)
204
Channel-0 Dead Zone Enable Register (PWMCH0DZER)
205
Channel-0 Dead Zone Counter Register (PWMCH0DZCR)
205
Register Map
206
Table 17 PWM Channel 0 Register Map and Reset Values
207
PWM Channel-1 Registers (Base Address : 0X4000_5100)
208
Channel-1 Interrupt Register(PWMCH1IR)
208
Channel-1 Interrupt Enable Register(PWMCH1IER)
208
Channel-1 Interrupt Clear Register(PWMCH1ICR)
209
Channel-1 Timer/Counter Register (PWMCH1TCR)
209
Channel-1 Prescale Counter Register (PWMCH1PCR)
210
Channel-1 Prescale Register (PWMCH1PR)
210
Channel-1 Match Register (PWMCH1MR)
211
Channel-1 Limit Register (PWMCH1LR)
211
Channel-1 Up-Down Mode Register (PWMCH1UDMR)
212
Channel-1 Timer/Counter Mode Register (PWMCH1TCMR)
212
Channel-1 PWM Output Enable and External Input Enable Register (PWMCH1PEEER)
213
Channel-1 Capture Mode Register (PWMCH1CMR)
213
Channel-1 Capture Register (PWMCH1CR)
213
Channel-1 Periodic Mode Register (PWMCH1PDMR)
214
Channel-1 Dead Zone Enable Register (PWMCH1DZER)
214
Channel-1 Dead Zone Counter Register (PWMCH1DZCR)
215
Register Map
216
PWM Channel-2 Registers (Base Address : 0X4000_5200)
217
Channel-2 Interrupt Register(PWMCH2IR)
217
Channel-2 Interrupt Enable Register(PWMCH2IER)
217
Channel-2 Interrupt Clear Register(PWMCH2ICR)
218
Channel-2 Timer/Counter Register (PWMCH2TCR)
218
Channel-2 Prescale Counter Register (PWMCH2PCR)
219
Channel-2 Prescale Register (PWMCH2PR)
219
Channel-2 Match Register (PWMCH2MR)
220
Channel-2 Limit Register (PWMCH2LR)
220
Channel-2 Up-Down Mode Register (PWMCH2UDMR)
220
Channel-2 Timer/Counter Mode Register (PWMCH2TCMR)
221
Channel-2 PWM Output Enable and External Input Enable Register (PWMCH2PEEER)
221
Channel-2 Capture Mode Register (PWMCH2CMR)
222
Channel-2 Capture Register (PWMCH2CR)
222
Channel-2 Periodic Mode Register (PWMCH2PDMR)
223
Channel-2 Dead Zone Enable Register (PWMCH2DZER)
223
Channel-2 Dead Zone Counter Register (PWMCH2DZCR)
224
Register Map
225
PWM Channel-3 Registers (Base Address : 0X4000_5300)
226
Channel-3 Interrupt Register(PWMCH3IR)
226
Channel-3 Interrupt Enable Register(PWMCH3IER)
226
Channel-3 Interrupt Clear Register(PWMCH3ICR)
227
Channel-3 Timer/Counter Register (PWMCH3TCR)
227
Channel-3 Prescale Counter Register (PWMCH3PCR)
228
Channel-3 Prescale Register (PWMCH3PR)
228
Channel-3 Match Register (PWMCH3MR)
229
Channel-3 Limit Register (PWMCH3LR)
229
Channel-3 Up-Down Mode Register (PWMCH3UDMR)
230
Channel-3 Timer/Counter Mode Register (PWMCH3TCMR)
230
Channel-3 PWM Output Enable and External Input Enable Register (PWMCH3PEEER)
231
Channel-3 Capture Mode Register (PWMCH3CMR)
231
Channel-3 Capture Register (PWMCH3CR)
231
Channel-3 Periodic Mode Register (PWMCH3PDMR)
232
Channel-3 Dead Zone Enable Register (PWMCH3DZER)
232
Channel-3 Dead Zone Counter Register (PWMCH3DZCR)
233
Register Map
234
PWM Channel-4 Registers (Base Address : 0X4000_5400)
235
Channel-4 Interrupt Register(PWMCH4IR)
235
Channel-4 Interrupt Enable Register(PWMCH4IER)
235
Channel-4 Interrupt Clear Register(PWMCH4ICR)
236
Channel-4 Timer/Counter Register (PWMCH4TCR)
236
Channel-4 Prescale Counter Register (PWMCH4PCR)
237
Channel-4 Prescale Register (PWMCH4PR)
237
Channel-4 Match Register (PWMCH4MR)
238
Channel-4 Limit Register (PWMCH4LR)
238
Channel-4 Up-Down Mode Register (PWMCH4UDMR)
238
Channel-4 Timer/Counter Mode Register (PWMCH4TCMR)
239
Channel-4 PWM Output Enable and External Input Enable Register (PWMCH4PEEER)
239
Channel-4 Capture Mode Register (PWMCH4CMR)
240
Channel-4 Capture Register (PWMCH4CR)
240
Channel-4 Periodic Mode Register (PWMCH4PDMR)
241
Channel-4 Dead Zone Enable Register (PWMCH4DZER)
241
Channel-4 Dead Zone Counter Register (PWMCH4DZCR)
242
Register Map
243
PWM Channel-5 Registers (Base Address : 0X4000_5500)
244
Channel-5 Interrupt Register(PWMCH5IR)
244
Channel-5 Interrupt Enable Register(PWMCH5IER)
244
Channel-5 Interrupt Clear Register(PWMCH5ICR)
245
Channel-5 Timer/Counter Register (PWMCH5TCR)
245
Channel-5 Prescale Counter Register (PWMCH5PCR)
246
Channel-5 Prescale Register (PWMCH5PR)
246
Channel-5 Match Register (PWMCH5MR)
247
Channel-5 Limit Register (PWMCH5LR)
247
Channel-5 Up-Down Mode Register (PWMCH5UDMR)
247
Channel-5 Timer/Counter Mode Register (PWMCH5TCMR)
248
Channel-5 PWM Output Enable and External Input Enable Register (PWMCH5PEEER)
248
Channel-5 Capture Mode Register (PWMCH5CMR)
249
Channel-5 Capture Register (PWMCH5CR)
249
Channel-5 Periodic Mode Register (PWMCH5PDMR)
250
Channel-5 Dead Zone Enable Register (PWMCH5DZER)
250
Channel-5 Dead Zone Counter Register (PWMCH5DZCR)
251
Register Map
252
PWM Channel-6 Registers (Base Address : 0X4000_5600)
253
Channel-6 Interrupt Register(PWMCH6IR)
253
Channel-6 Interrupt Enable Register(PWMCH6IER)
253
Channel-6 Interrupt Clear Register(PWMCH6ICR)
254
Channel-6 Timer/Counter Register (PWMCH6TCR)
254
Channel-6 Prescale Counter Register (PWMCH6PCR)
255
Channel-6 Prescale Register (PWMCH6PR)
255
Channel-6 Match Register (PWMCH6MR)
256
Channel-6 Limit Register (PWMCH6LR)
256
Channel-6 Up-Down Mode Register (PWMCH6UDMR)
257
Channel-6 Timer/Counter Mode Register (PWMCH6TCMR)
257
Channel-6 PWM Output Enable and External Input Enable Register (PWMCH6PEEER)
258
Channel-6 Capture Mode Register (PWMCH6CMR)
258
Channel-6 Capture Register (PWMCH6CR)
258
Channel-6 Periodic Mode Register (PWMCH6PDMR)
259
Channel-6 Dead Zone Enable Register (PWMCH6DZER)
259
Channel-6 Dead Zone Counter Register (PWMCH6DZCR)
260
Register Map
261
PWM Channel-7 Registers (Base Address : 0X4000_5700)
262
Channel-7 Interrupt Register(PWMCH7IR)
262
Channel-7 Interrupt Enable Register(PWMCH7IER)
262
Channel-7 Interrupt Clear Register(PWMCH7ICR)
263
Channel-7 Timer/Counter Register (PWMCH7TCR)
263
Channel-7 Prescale Counter Register (PWMCH7PCR)
264
Channel-7 Prescale Register (PWMCH7PR)
264
Channel-7 Match Register (PWMCH7MR)
265
Channel-7 Limit Register (PWMCH7LR)
265
Channel-7 Up-Down Mode Register (PWMCH7UDMR)
266
Channel-7 Timer/Counter Mode Register (PWMCH7TCMR)
266
Channel-7 PWM Output Enable and External Input Enable Register (PWMCH7PEEER)
267
Channel-7 Capture Mode Register (PWMCH7CMR)
267
Channel-7 Capture Register (PWMCH7CR)
267
Channel-7 Periodic Mode Register (PWMCH7PDMR)
268
Channel-7 Dead Zone Enable Register (PWMCH7DZER)
268
Channel-7 Dead Zone Counter Register (PWMCH7DZCR)
269
Register Map
270
PWM Common Registers (Base Address : 0X4000_5800)
271
Interrupt Enable Register (IER)
271
Start/Stop Register (SSR)
272
Pause Register (PSR)
273
Register Map
274
22 Dual Timers
275
Introduction
275
Features
275
Functional Description
276
Clock and Clock Enable
276
Timer Size
276
Prescaler
276
Repetition Mode
276
Interrupt
277
Operation
277
How to Set the Dual Timers
278
Dual Timer0_0 Registers (Base Address : 0X4000_1000)
279
Timer0_0 Load Register(Dualtimer0_0Timerload)
279
Timer0_0 Value Register(Dualtimer0_0Timervalue)
279
Timer0_0 Control Register(Dualtimer0_0Timercontrol)
279
Timer0_0 Interrupt Clear Register (Dualtimer0_0Timerintclr)
280
Timer0_0 Raw Interrupt Status Register (Dualtimer0_0Timerris)
280
Timer0_0 Masked Interrupt Status Register (Dualtimer0_0Timermis)
281
Timer0_0 Background Load Register (Dualtimer0_0Timerbgload)
281
Register Map
283
Dual Timer0_1 Registers (Base Address : 0X4000_1020)
284
Timer0_1 Load Register(Dualtimer0_1Timerload)
284
Timer0_1 Value Register(Dualtimer0_1Timervalue)
284
Timer0_1 Control Register(Dualtimer0_1Timercontrol)
284
Timer0_1 Interrupt Clear Register (Dualtimer0_1Timerintclr)
285
Timer0_1 Raw Interrupt Status Register (Dualtimer0_1Timerris)
285
Timer0_1 Masked Interrupt Status Register (Dualtimer0_1Timermis)
286
Timer0_1 Background Load Register (Dualtimer0_1Timerbgload)
286
Register Map
288
Dual Timer 0 Clock Enable Register (Base Address : 0X4000_1080)
289
Timer0_0 Clock Enable Register (TIMCLKEN0_0)
289
Timer0_1 Clock Enable Register (TIMCLKEN0_1)
289
Register Map
290
Dual Timer1_0 Registers (Base Address : 0X4000_2000)
291
Timer1_0 Load Register(Dualtimer1_0Timerload)
291
Timer1_0 Value Register(Dualtimer1_0Timervalue)
291
Timer1_0 Control Register(Dualtimer1_0Timercontrol)
291
Timer1_0 Interrupt Clear Register (Dualtimer1_0Timerintclr)
292
Timer1_0 Raw Interrupt Status Register (Dualtimer1_0Timerris)
292
Timer1_0 Masked Interrupt Status Register (Dualtimer1_0Timermis)
293
Timer1_0 Background Load Register (Dualtimer1_0Timerbgload)
293
Register Map
295
Dual Timer1_1 Registers (Base Address : 0X4000_2020)
296
Timer1_1 Load Register(Dualtimer1_1Timerload)
296
Timer1_1 Value Register(Dualtimer1_1Timervalue)
296
Timer1_1 Control Register(Dualtimer1_1Timercontrol)
296
Timer1_1 Interrupt Clear Register (Dualtimer1_1Timerintclr)
297
Timer1_1 Raw Interrupt Status Register (Dualtimer1_1Timerris)
297
Timer1_1 Masked Interrupt Status Register (Dualtimer1_1Timermis)
298
Timer1_1 Background Load Register (Dualtimer1_1Timerbgload)
298
Register Map
300
Dual Timer 1 Clock Enable Register (Base Address : 0X4000_2080)
301
Timer1_0 Clock Enable Register (TIMCLKEN1_0)
301
Timer1_1 Clock Enable Register (TIMCLKEN1_1)
301
Register Map
302
23 Watchdog Timer
302
Introduction
302
Features
302
Functional Description
302
Clock
302
Interrupt and Reset Request
303
Watchdog Timer Registers (Base Address : 0X4000_0000)
303
Watchdog Timer Load Register(Wdtload)
303
Watchdog Timer Value Register(Wdtvalue)
304
Watchdog Timer Control Register(Wdtcontrol)
304
Watchdog Timer Interrupt Clear Register (Wdtintclr)
304
Watchdog Timer Raw Interrupt Status Register (WDTRIS)
305
Watchdog Timer Masked Interrupt Status Register (WDTMIS)
305
Watchdog Timer Lock Register(Wdtlock)
306
Register Map
307
24 Real-Time Clock(RTC)
307
Introduction
307
Features
307
Functional Description
307
RTC Clock
308
RTC Interrupt
308
RTC Counter and Calendar
308
RTC Setting Flow
309
RTC Registers (Base Address : 0X4000_E000)
310
RTC Control Register (RTCCON)
310
RTC Interrupt Mask Register (RTCINTE)
311
RTC Interrupt Pending Register (RTCINTP)
313
RTC Alarm Mask Register (RTCAMR)
314
RTC BCD Second Register (BCDSEC)
315
RTC BCD Minute Register (BCDMIN)
315
RTC BCD Hour Register (BCDHOUR)
315
RTC BCD Day Register (BCDDAY)
316
RTC BCD Date Register (BCDDATE)
316
RTC BCD Month Register (BCDMON)
316
RTC BCD Year Register (BCDYEAR)
317
RTC Predetermining Second Register (PRESEC)
317
RTC Predetermining Minute Register (PREMIN)
317
RTC Predetermining Hour Register (PREHOUR)
318
RTC Predetermining Day Register (PREDAY)
318
RTC Predetermining Date Register (PREDATE)
318
RTC Predetermining Month Register (PREMON)
319
RTC Predetermining Year Register (PREYEAR)
319
RTC Consolidated Time0 Register (RTCTIME0)
319
RTC Consolidated Time1 Register (RTCTIME1)
320
Register Map
321
25 Uart(Universal Asynchronous Receive Transmit)
322
Introduction
322
Features
322
Functional Description
323
Baud Rate Calculation
325
Data Transmission
326
Data Receive
326
Hardware Flow Control
327
UART0 Registers(Base Address: 0X4000_C000)
328
UART0DR (UART0 Data Register)
328
UART0RSR/ECR (UART0 Receive Status Register/Error Clear Register)
329
UART0FR (UART0 Flag Register)
330
UART0ILPR (UART0 Irda Low-Power Counter Register)
331
UART0IBRD (UART0 Integer Baud Rate Register)
332
UART0FBRD (UART0 Fractional Baud Rate Register)
332
UART0LCR_H (UART0 Line Control Register)
333
UART0CR (UART0 Control Register)
334
UART0IFLS (UART0 Interrupt FIFO Level Select Register)
336
UART0IMSC (UART0 Interrupt Mask Set/Clear Register)
336
UART0RIS (UART0 Raw Interrupt Status Register)
338
UART0MIS (UART0 Masked Interrupt Status Register)
339
UART0ICR (UART0 Interrupt Clear Register)
340
Register Map
341
UART1 Registers(Base Address: 0X4000_D000)
342
UART1DR (UART1 Data Register)
342
UART1RSR/ECR (UART1 Receive Status Register/Error Clear Register)
342
UART1FR (UART1 Flag Register)
343
UART1ILPR (UART1 Irda Low-Power Counter Register)
344
UART1IBRD (UART1 Integer Baud Rate Register)
345
UART1FBRD (UART1 Fractional Baud Rate Register)
345
UART1LCR_H (UART1 Line Control Register)
346
UART1CR (UART1 Control Register)
347
UART1IFLS (UART1 Interrupt FIFO Level Select Register)
349
UART1IMSC (UART1 Interrupt Mask Set/Clear Register)
349
UART1RIS (UART1 Raw Interrupt Status Register)
351
UART1MIS (UART1 Masked Interrupt Status Register)
352
UART1ICR (UART1 Interrupt Clear Register)
353
Register Map
354
26 Universal Asynchronous Receive Transmit(UART2)
355
Introduction
355
Feature
355
Functional Description
355
Baud Rate Calculation
355
UART2 Registers(Base Address: 0X4000_6000)
357
UART2DR (UART2 Data Register)
357
UART2SR (UART2 Status Register)
357
UART2CR (UART2 Control Register)
358
UART2ISR/ICR (UART2 Interrupt Status/Interrupt Clear Register)
358
UART2BDR (UART2 Baud Rate Divider Register)
359
Register Map
360
27 Synchronous Serial Port (SSP)
361
Introduction
361
Features
361
Functional Description
362
Clock Prescaler
362
Transmit FIFO
362
Receive FIFO
363
Interrupt Generation Logic
363
DMA Interface
363
Table 37 DMA Trigger Points for the Transmit and Receive Fifos
364
Interface Reset
365
Configuring the SSP
365
Enable Primecell SSP Operation
366
Clock Ratios
366
Programming the SSPCR0 Control Register
367
Programming the SSPCR1 Control Register
367
Frame Format
368
Texas Instruments Synchronous Serial Frame Format
369
Motorola SPI Frame Format
370
National Semiconductor Microwire Frame Format
376
Master and Slave Configurations
378
SSP Flow Chart
379
SSP0 Registers (Base Address : 0X4000_A000)
380
SSP0 Control Register 0 (SSP0CR0)
380
SSP0 Control Register 1 (SSP0CR1)
382
SSP0 Data Register (SSP0DR)
382
SSP0 Status Register (SSP0SR)
383
SSP0 Clock Prescale Register (SSP0CPSR)
384
SSP0 Interrupt Mask Set or Clear Register (SSP0IMSC)
384
SSP0 Raw Interrupt Status Register (SSP0RIS)
385
SSP0 Masked Interrupt Status Register, (SSP0MIS)
385
SSP0 Interrupt Clear Register (SSP0ICR)
386
SSP0 DMA Control Register, (SSP0DMACR)
386
Register Map
388
SSP1 Registers (Base Address : 0X4000_B000)
389
SSP1 Control Register 0 (SSP1CR0)
389
SSP1 Control Register 1 (SSP1CR1)
390
SSP1 Data Register (SSP1DR)
392
SSP1 Status Register (SSP1SR)
392
SSP1 Clock Prescale Register (SSP1CPSR)
393
SSP1 Interrupt Mask Set or Clear Register (SSP1IMSC)
393
SSP1 Raw Interrupt Status Register (SSP1RIS)
394
SSP1 Masked Interrupt Status Register, (SSP1MIS)
394
SSP1 Interrupt Clear Register (SSP1ICR)
395
SSP1 DMA Control Register, (SSP1DMACR)
395
Register Map
397
Document History Information
398
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Wiznet W7500P Information (6 pages)
Revision information
Brand:
Wiznet
| Category:
Microcontrollers
| Size: 0.4 MB
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