Wiznet W7500 Reference Manual page 26

List of figures
Figure 1 W7500 System Architecture .......................................................... 32
Figure 2 W7500 memory map ................................................................... 34
Figure 3 POR reset waveform ................................................................... 38
Figure 4 TOE block diagram ..................................................................... 43
Figure 5. Register & Memory Organization ................................................... 45
Figure 6. operation of boot code .............................................................. 84
Figure 7. Flash reading sequence .............................................................. 88
Figure 8. Flash erase operations ............................................................... 89
Figure 9. main Flash memory programming sequence ..................................... 90
Figure 10 CRG block diagram ................................................................... 93
Figure 11. Random Number Generator block diagram .................................... 117
Figure 12. Flow chart of RNG operation ..................................................... 118
Figure 13. External Interrupt diagram ....................................................... 156
Figure 14. function schematic of digital I/O pad .......................................... 189
Figure 15. function schematic of digital/analog mux IO pad ............................ 190
Figure 16. GPIO block diagram ................................................................ 232
Figure 17. GPIO Flow chart .................................................................... 233
Figure 18. MASK LOWBYTE access ............................................................ 234
Figure 19 MASK HIGHBYTE access ............................................................. 234
Figure 20. DMA Block diagram ................................................................. 267
Figure 21. DMA ping pong cycle ............................................................... 271
Figure 22. ADC block diagram ................................................................. 284
Figure 23. The ADC operation flowchart with non-interrupt ............................. 285
Figure 24. The ADC operation flowchart with interrupt .................................. 286
Figure 25 PWM block diagram ................................................................. 291
Figure 26 Periodic mode ........................................................................ 293
Figure 27 one-shot mode ....................................................................... 293
Figure 28 Up-count mode ...................................................................... 293
Figure 29 Down-count mode ................................................................... 293
Figure 30 Counter mode with rising edge ................................................... 294
Figure 31 Counter mode with falling edge .................................................. 294
Figure 32 Counter mode with rising and falling edge ..................................... 295
Figure 33 Timer/Counter timing diagram with match interrupt ........................ 295
Figure 34 Timer/Counter timing diagram with overflow interrupt ..................... 296
Figure 35 The PWM output up to match register ........................................... 297
Figure 36 The PWM output up to limit register ............................................. 297
Figure 37 PWM waveform with dead zone time ............................................ 298
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W7500 Datasheet Version1.0.0