Ssp1 Raw Interrupt Status Register (Ssp1Ris); Ssp1 Masked Interrupt Status Register, (Ssp1Mis) - Wiznet W7500 Reference Manual

1 : Receive FIFO written to while full condition interrupt is not masked.
[1] RTIM – Receive timeout interrupt mask:
0 : Receive FIFO not empty and no read prior to timeout period interrupt is
masked.
1 : Receive FIFO not empty and no read prior to timeout period interrupt is
not masked.
[2] RXIM – Receive FIFO interrupt mask:
0 : Receive FIFO half full or less condition interrupt is masked.
1 : Receive FIFO half full or less condition interrupt is not masked.
[3] TXIM – Transmit FIFO interrupt mask:
0 : Transmit FIFO half empty or less condition interrupt is masked.
1 : Transmit FIFO half empty or less condition interrupt is not masked.
23.6.7

SSP1 Raw interrupt status register (SSP1RIS)

Address offset: 0x0018
Reset value: 0x0000_00004
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] RORRIS – Gives the raw interrupt state, prior to masking, of the SSPRORINTR
interrupt
[1] RTRIS – Gives the raw interrupt state, prior to masking, of the SSPRTINTR
interrupt
[2] RXRIS – Gives the raw interrupt state, prior to masking, of the SSPRXINTR
interrupt
[3] TXRIS – Gives the raw interrupt state, prior to masking, of the SSPTXINTR
interrupt
23.6.8

SSP1 Masked interrupt status register, (SSP1MIS)

Address offset: 0x001C
Reset value: 0x0000_00000
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res res
19 18 17 16
res res res res
3 2 1 0
TXRI RXRI RTRI ROR
S S S RIS
R/W R/W R/W R/W
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