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22.3.2
Data transmission
Data transmitted is stored in a 32-byte FIFOs. Transmit data is written into the transmit FIFO
for transmission. If UART is enabled, it causes a data frame to start transmitting with
parameters indicated in the UARTxLCR_H.
Data continues to transmit until there is no data left in the transmit FIFO. The BUSY bit of
UARTxFR is „1‟ as soon as data is written to the transmit FIFO, which means the FIFO is not
empty, and remains as „1‟ while data is being transmitted.
22.3.3
Data receive
Received data is stored in the 32-byte FIFOs. When a start bit has been received, it begins
running and data is sampled on the eighth cycle of that counter in UART mode. A valid stop
bit is confirmed if UARTRXD is „1‟. When a full word is received, the data is stored in the
receive FIFO. Error bit is stored in bit[10:8] of UARTxCR and overrun is stored in bit[11] of
UARTxCR.
W7500 Datasheet Version1.0.0
Initia l setting
Set RTS/CTS of UARTxCR
Set FEN of UARTxLCR_H
Set RxSel/TxSel of UARTxIFLS
TX
Send Tx da ta
Figure 61. Transmit and Receive data flow chart
RX
receive Rx da ta
END
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