Wiznet W7500 Reference Manual page 453

Internet offload processor
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15
14
13
12
res
res
res
res
[7] SPS – Stick parity select
0: stick parity is disable
1: either:
The parity bit is transmitted and checked as a 1 when EPS bit set „0‟
The parity bit is transmitted and checked as a 0 when EPS bit set „1‟
[6:5] WLEN – Word length
[4] FEN – Enable FIFO
0: The FIFO become 1-byte-deep holding register.
1: The transmit and receive FIFO buffers are enable (FIFO mode)
[3] STP2 – Two stop bit select
1: Two stop bits are transmitted at the end of the frame
[2] EPS – Even parity select
0: odd parity.
1: even parity
[1] PEN – Parity enable
0: parity is disabled and no parity bit added to the data frame
1: parity checking and generations is enabled
[0] BRK – Send break
0: For normal use, the bit must be cleared to 0
1: The low-level is continually output on the UARTTXD output
PEN
EPS
SPS
0
X
1
1
1
0
1
0
1
1
W7500 Datasheet Version1.0.0
11
10
9
res
res
res
00
01
5 bits
6 bits
Parity bit(Transmitted or checked)
X
0
0
1
1
8
7
6
5
res
SPS
WLEN
R/W
10
11
7 bits
8 bits
Not transmitted or checked
Even parity
Odd parity
1
0
4
3
2
1
FEN
STP2
EPS
PEN
453 / 512
0
BRK

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