Wiznet W7500 Reference Manual page 23

23.6.8 SSP1 Masked interrupt status register, (SSP1MIS) ............................ 508
23.6.9 SSP1 Interrupt clear register (SSP1ICR) ........................................ 509
23.6.10 SSP1 DMA control register, (SSP1DMACR) ...................................... 509
23.7 Register map ............................................................................... 511
Document History Information ....................................................................... 512
W7500 Datasheet Version1.0.0
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