Channel-4 Interrupt Clear Register(Pwmch4Icr); Channel-4 Timer/Counter Register (Pwmch4Tcr) - Wiznet W7500 Reference Manual

[0] MIE – Match Interrupt Enabled.
O : Match interrupt is not enabled.
1 : Match interrupt is enabled.
[1] OIE – Overflow Interrupt Enable.
O : Overflow interrupt is not enabled.
1 : Overflow interrupt is enabled.
[2] CIE – Capture Interrupt Enable.
O : Capture interrupt is not enabled.
1 : Capture interrupt is enabled.
18.12.3

Channel-4 interrupt clear register(PWMCH4ICR)

Base address : 0x4000_5400
Address offset : 0x08
31 30 29 28
res res res res
15 14 13 12
res res res res
This bit is set by software, cleared by hardware when a capture interrupt becomes 0.
[0] MIC – Match Interrupt
O : No action.
1 : Match interrupt is cleared.
[1] OIC – Overflow Interrupt
O : No action.
1 : Overflow Interrupt is cleared.
[2] CIC – Capture Interrupt Clear.
O : No action.
1 : Capture Interrupt is cleared.
18.12.4

Channel-4 Timer/Counter Register (PWMCH4TCR)

Base address : 0x4000_5400
Address offset : 0x0C
Reset value : 0x0000_0000
31
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21
res res res
7 6 5
res res res
TCR
20 19 18 17
res res res res
4 3 2 1
res res CIC OIC
W W
339 / 512
16
res
0
MIC
W
0