Wiznet W7500 Reference Manual page 18

18.20 PWM Common Registers (Base address : 0x4000_5800) ............................ 374
18.20.1 Interrupt Enable Register (IER).................................................. 374
18.20.2 Start/Stop Register (SSR)......................................................... 375
18.20.3 Pause Register (PSR) .............................................................. 376
18.21 Register map ............................................................................... 377
19 Dual timers ........................................................................................... 378
19.1 Introduction ................................................................................ 378
19.2 Features .................................................................................... 378
19.3 Functional description ................................................................... 379
19.3.1 Clock and clock enable ........................................................... 379
19.3.2 Timer size ........................................................................... 379
19.3.3 Prescaler ............................................................................ 379
19.3.4 Repetition mode ................................................................... 379
19.3.5 Interrupt ............................................................................ 380
19.3.6 Operation ........................................................................... 380
19.3.7 How to set the dual timers ...................................................... 381
19.4 Dual timer0_0 Registers (Base address : 0x4000_1000) ............................ 382
19.4.1 Timer0_0 Load Register(DUALTIMER0_0TimerLoad) ......................... 382
19.4.2 Timer0_0 Value Register(DUALTIMER0_0TimerValue)........................ 382
19.4.3 Timer0_0 Control Register(DUALTIMER0_0TimerControl) ................... 382
19.4.4 Timer0_0 Interrupt Clear Register (DUALTIMER0_0TimerIntClr) ........... 383
19.4.5 Timer0_0 Raw Interrupt Status Register (DUALTIMER0_0TimerRIS) ....... 384
19.4.6 Timer0_0 Masked Interrupt Status Register (DUALTIMER0_0TimerMIS) .. 384
19.4.7 Timer0_0 Background Load Register (DUALTIMER0_0TimerBGLoad) ...... 385
19.5 Register map ............................................................................... 386
19.6 Dual timer0_1 Registers (Base address : 0x4000_1020) ............................ 387
19.6.1 Timer0_1 Load Register(DUALTIMER0_1TimerLoad) ......................... 387
19.6.2 Timer0_1 Value Register(DUALTIMER0_1TimerValue)........................ 387
19.6.3 Timer0_1 Control Register(DUALTIMER0_1TimerControl) ................... 387
19.6.4 Timer0_1 Interrupt Clear Register (DUALTIMER0_1TimerIntClr) ........... 388
19.6.5 Timer0_1 Raw Interrupt Status Register (DUALTIMER0_1TimerRIS) ....... 388
19.6.6 Timer0_1 Masked Interrupt Status Register (DUALTIMER0_1TimerMIS) .. 389
19.6.7 Timer0_1 Background Load Register (DUALTIMER0_1TimerBGLoad) ...... 389
19.7 Register map ............................................................................... 391
19.8 Dual Timer 0 Clock Enable Register (Base address : 0x4000_1080) .............. 392
19.8.1 Timer0_0 Clock Enable Register (TIMCLKEN0_0) ............................. 392
19.8.2 Timer0_1 Clock Enable Register (TIMCLKEN0_1) ............................. 392
19.9 Register map ............................................................................... 393
19.10 Dual timer1_0 Registers (Base address : 0x4000_2000) ............................ 394
W7500 Datasheet Version1.0.0
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