22
UART(Universal Asynchronous Receive Transmit)
22.1
Introduction
The UART supports synchronous one-way communication, half-duplex single wire
communication, and multiprocessor communications(CTS/RTS).
22.2
Features
Serial-to-parallel conversion on data received from a peripheral device
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Parallel-to-serial conversion on data transmitted to the peripheral device
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Data size of 5,6,7 and 8 its
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One or two stop bits
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Even, odd, stick, or no-parity bit generation and detection
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Support of hardware flow control
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Programmable FIFO disabling for 1-byte depth.
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Programmable use of UART or IrDA SIR input/output
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False start bit detection
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22.3
Functional description
UART bidirectional communication requires a minimum of two pins: RX, TX
The frame are comprised of:
An Idle Line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
1, 1.5, 2 Stop bits indicating that the frame is complete
The USART interface uses a baud rate generator
A status register (UART1_RISR)
data registers (UART1DR)
A baud rate register (UART1_IBRD,UART1_FBRD)
W7500 Datasheet Version1.0.0
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