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21.3
Functional description ................................................................... 412
21.3.1
Data validity ........................................................................ 413
21.3.2
Acknowledge ....................................................................... 414
21.3.3
Bit Command Controller .......................................................... 414
21.3.4
Slave address ....................................................................... 415
21.3.5
Read/Write bit ..................................................................... 415
21.3.6
Acknowledge(ACK) and Not Acknowledge(NACK) ............................ 416
21.3.7
Data transfer ....................................................................... 416
21.3.8
Operating Modes ................................................................... 416
21.3.9
Interrupts ........................................................................... 417
21.3.10
Master mode ........................................................................ 418
21.3.11
Slave mode ......................................................................... 421
21.4
I2C0 Registers(Base address: 0x4000_8000) .......................................... 422
21.4.1
I2C0 Prescaler Register(I2C0_PRER) ............................................ 422
21.4.2
I2C0 Control Register(I2C0_CTR) ................................................ 423
21.4.3
I2C0 Command Register(I2C0_CMDR) .......................................... 424
21.4.4
I2C0 Status Register(I2C0_SR) ................................................... 424
21.4.5
I2C0 Timeout Set Register(I2C0_TSR) .......................................... 426
21.4.6
I2C0 Slave Address Register(I2C0_SADDR) ..................................... 426
21.4.7
I2C0 Transmit Register(I2C0_TXR) .............................................. 427
21.4.8
I2C0 Receive Register(I2C0_RXR) ............................................... 427
21.4.9
I2C0 Interrupt Status Register(I2C0_ISR) ...................................... 428
21.4.10
I2C0 Interrupt Status Clear Register(I2C0_ISCR) ............................. 428
21.4.11
I2C0 Interrupt Status Mask Register(I2C0_ISMR) ............................. 429
21.5
Register map ............................................................................... 431
21.6
I2C1 Registers(Base address : 0x4000_9000) ......................................... 432
21.6.1
I2C1 Prescaler Register(I2C1_PRER) ............................................ 432
21.6.2
I2C1 Control Register(I2C1_CTR) ................................................ 433
21.6.3
I2C1 Command Register(I2C1_CMDR) .......................................... 434
21.6.4
I2C1 Status Register(I2C1_SR) ................................................... 434
21.6.5
I2C1 Timeout Set Register(I2C1_TSR) .......................................... 436
21.6.6
I2C1 Slave Address Register(I2C1_SADDR) ..................................... 436
21.6.7
I2C1 Transmit Register(I2C1_TXR) .............................................. 437
21.6.8
I2C1 Receive Register(I2C1_RXR) ............................................... 437
21.6.9
I2C1 Interrupt Status Register(I2C1_ISR) ...................................... 438
21.6.10
I2C1 Interrupt Status Clear Register(I2C1_ISCR) ............................. 438
21.6.11
I2C1 Interrupt Status Mask Register(I2C1_ISMR) ............................. 439
21.7
Register map ............................................................................... 441
22 UART(Universal Asynchronous Receive Transmit) ............................................ 442
W7500 Datasheet Version1.0.0
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