Ssp1 Interrupt Clear Register (Ssp1Icr); Ssp1 Dma Control Register, (Ssp1Dmacr) - Wiznet W7500 Reference Manual

Internet offload processor

Hide thumbs Also See for W7500:

Table of Contents

[0] RORMIS – Gives the receive over run masked interrupt status, after masking, of

the SSPRORINTR interrupt

[1] RTMIS – Gives the receive timeout masked interrupt state, after masking, of the

SSPRTINTR interrupt

[2] RXMIS – Gives the receive FIFO masked interrupt state, after masking, of the

SSPRXINTR interrupt

[3] TXMIS – Gives the transmit FIFO masked interrupt state, after masking, of the

SSPTXINTR interrupt

SSP1 Interrupt clear register (SSP1ICR)

Address offset: 0x0020

Reset value: 0x0000_00000

[0] RORICS – Clears the SSPRORINTR interrupt

[1] RTIC – Clears the SSPRTINTR interrupt

Address offset: 0x0024

Reset value: 0x0000_00000

W7500 Datasheet Version1.0.0