Register Map; Table 37 I2C0 Register Map And Reset Values - Wiznet W7500 Reference Manual

21.5

Register map

The following Table 37 summarizes the I2C0 registers.
Offset Register
I2C0PRER
0x00
reset value
I2C0CTR
0x04
reset value
I2C0CMD
0x08
reset value
I2C0SR
0x0C
reset value
I2C0TO
0x10
reset value
I2C0ADDR
0x14
reset value
I2C0TXR
0x18
reset value
I2C0RXR
0x1C
reset value
I2C0ISR
0x20
reset value
I2C0ISCR
0x24
reset value
I2C0ISMR
0x28
reset value
W7500 Datasheet Version1.0.0

Table 37 I2C0 register map and reset values

0 0
1 1
COUNT
0 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 0
COUNT
1 1 1 1 1 1 1 1 1 1 1
ADDR
0 0 0 0 0
Transmit Data
1 1 1 1 1
Receive Data
0 0 0 0 0
0 0
0 0
비고
SCL/SCH Register
1 0 0
Control Register
0
Command Register
Status Register
0 0
Timeout Register
1 1 1
Slave address Register
0 0 0
Transmit Register
1 1 1
Receive Register
0 0 0
Interrupt Status Register
0 0 0
Interrupt Status Clear Register
0
Interrupt Status Mask Register
0 0 0
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