Wiznet W7500 Reference Manual page 12

15.8.5 GPIOC Interrupt Enable Set Register(GPIOC_ INTENSET) ................... 252
15.8.6 GPIOC Interrupt Enable Clear Register(GPIOC_ INTENCLR) ................ 253
15.8.7 GPIOC Interrupt Type Set Register(GPIOC_ INTTYPESET) ................... 253
15.8.8 GPIOC Interrupt Type Clear Register(GPIOC_ INTTYPECLR) ................ 254
15.8.9 GPIOC Interrupt Polarity Set Register(GPIOC_ INTPOLSET) ................ 254
15.8.10 GPIOC Interrupt Polarity Clear Register(GPIOC_ INTPOLCLR) ............. 255
15.8.11 GPIOC Interrupt Status/Interrupt Clear Register(GPIOC_ INTSTATUS/
INTCLEAR) 256
15.8.12 GPIOC Lower Byte Masked Access Register(GPIOC_ LB_MASKED) ......... 256
15.8.13 GPIOC Upper Byte Masked Access Register(GPIOC_ UB_MASKED) ......... 257
15.9 Register map ............................................................................... 258
15.10 GPIOD Registers(Address Base: 0x4500_0000) ....................................... 259
15.10.1 GPIOD Data Register(GPIOD_DATA) ............................................. 259
15.10.2 GPIOD Output Latch Register(GPIOD_DATAOUT) ............................. 259
15.10.3 GPIOD Enable Set Register(GPIOD_OUTENSET) ............................... 259
15.10.4 GPIOD Enable Clear Register(GPIOD_OUTENCLR) ............................ 260
15.10.5 GPIOD Interrupt Enable Set Register(GPIOD_ INTENSET) ................... 260
15.10.6 GPIOD Interrupt Enable Clear Register(GPIOD_ INTENCLR) ................ 261
15.10.7 GPIOD Interrupt Type Set Register(GPIOD_ INTTYPESET) ................... 261
15.10.8 GPIOD Interrupt Type Clear Register(GPIOD_ INTTYPECLR) ................ 262
15.10.9 GPIOD Interrupt Polarity Set Register(GPIOD_ INTPOLSET) ................ 262
15.10.10 GPIOD Interrupt Polarity Clear Register(GPIOD_ INTPOLCLR) ............. 263
15.10.11 GPIOD Interrupt Status/Interrupt Clear Register(GPIOD_ INTSTATUS/
INTCLEAR) 264
15.10.12 GPIOD Lower Byte Masked Access Register(GPIOD_ LB_MASKED) ......... 264
15.10.13 GPIOD Upper Byte Masked Access Register(GPIOD_ UB_MASKED) ......... 265
15.11 Register map ............................................................................... 266
16 Direct memory access controller (DMA) ........................................................ 267
16.1 Introduction ................................................................................ 267
16.2 Features .................................................................................... 267
16.3 Functional description ................................................................... 267
16.3.1 DMA request mapping ............................................................. 268
16.3.2 DMA arbitration .................................................................... 268
16.3.3 DMA cycle types .................................................................... 268
16.4 Registers (Base address : 0x4100_4000) ............................................... 272
16.4.1 DMA status register (DMA_STATUS) ............................................. 272
16.4.2 DMA configuration register (DMA_CFG) ........................................ 272
16.4.3 DMA control data base pointer register (DMA_CTRL_BASE_PTR) .......... 273
W7500 Datasheet Version1.0.0
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