Figure 74. Motorola Spi Frame Format, Single And Continuous Transfers, With Spo - Wiznet W7500 Reference Manual

continuous transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period
after the last bit has been captured.
Figure 74 shows the transfer signal sequence for Motorola SPI format with SPO=1, SPH=1, and
it covers both single and continuous transfers. In Figure 10, Q is an undefined signal.
SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPRXD
nSSPOE
SSPTXD
Figure 74.
Motorola SPI frame format, single and continuous transfers, with SPO=1 and SPH=1
In this configuration, during idle periods:
• the SSPCLKOUT signal is forced HIGH
• the SSPFSSOUT signal is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance
• when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW,
enabling the SSPCLKOUT pad, active-LOW enable
• when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH,
disabling the SSPCLKOUT pad, active-LOW enable.
If the PrimeCell SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line
is driven LOW, enabling the master SSPTXD output pad. After an additional one half
SSPCLKOUT period, both master and slave data are enabled onto their respective
transmission lines. At the same time, the SSPCLKOUT is enabled with a falling edge transition.
Data is then captured on the rising edges and propagated on the falling edges of the
SSPCLKOUT signal.
After all bits have been transferred in the case of a single word transmission, the SSPFSSOUT
line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been
captured.
W7500 Datasheet Version1.0.0
Q
MSB
MSB MSB
4 to 16 bits
LSB LSB Q
LSB LSB
490 / 512