I2C0 Timeout Set Register(I2C0_Tsr); I2C0 Slave Address Register(I2C0_Saddr) - Wiznet W7500 Reference Manual

21.4.5

I2C0 Timeout Set Register(I2C0_TSR)

Address offset: 0x10
Reset value: 0x0000_FFFF
31 30 29 28
res res res res
15 14 13 12
[15:0] TSR - Time Set
This register configures the retransmission timeout period. The default value is
„0xFFFF‟.
[31:16] Reserved, must be kept at reset value
21.4.6

I2C0 Slave Address Register(I2C0_SADDR)

Address offset: 0x14
Reset value: 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res Res res res
[0] SADDR – Slave address bit 0
7-bit addressing mode(ADDR10=0)
CTREN = 0 : It indicates a R/W bit
CTREN = 1 : This bit are don‟t care
[7:1] SADDR[7:1] – Slave address bit 7:1
7-bit addressing mode (ADDR10=0)
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21
res res res
7 6 5
TSR
R/W
23 22 21
res res res
7 6 5
20 19 18 17
res res res res
4 3 2 1
20 19 18 17
res res res res
4 3 2 1
SADDR
R/W
426 / 512
16
res
0
16
res
0