Page 2: Table Of Contents
6.4.2 SysTick Reload Value Register (SYST_RVR) ........41 6.4.3 SysTick Current Value Register (SYST_CVR) ........42 6.4.4 SysTick Calibration Value Register (SYST_CALIB) ......42 7 TCPIPCore Offload Engine (TOE) ..............43 Introduction ................. 43 2 / 512 W7500 Datasheet Version1.0.0...
Page 3 Sn_ICR (Socket n Interrupt Clear Register) ........68 7.6.6 Sn_SR (Socket n Status Register) ..........69 7.6.7 Sn_PNR (Socket n Protocol Number Register) ......... 71 7.6.8 Sn_TOSR (Socket n IP Type of Service Register) ....... 71 3 / 512 W7500 Datasheet Version1.0.0...
Page 4 10.2.1 Reset .................. 92 10.2.2 Clock .................. 92 10.3 Functional description ..............93 10.3.1 External Oscillator Clock ............93 10.3.2 RC oscillator clock ..............94 10.3.3 PLL ..................94 10.3.4 Generated clock ..............94 4 / 512 W7500 Datasheet Version1.0.0...
Page 5 10.4.34 WDOGCLK High Speed prescale value select register (WDOGCLK_HS_PVSR) 10.4.35 UARTCLK source select register (UARTCLK_SSR) ......111 10.4.36 UARTCLK prescale value select register (UARTCLK_PVSR) ....112 10.4.37 MIICLK enable control register (MIICLK_ECR) ......... 112 5 / 512 W7500 Datasheet Version1.0.0...
Page 6 PA_15 pad alternate function select register (PA_15_AFR) ....132 12.4.17 PB_00 pad alternate function select register (PB_00_AFR) ....133 12.4.18 PB_01 pad alternate function select register (PB_01_AFR) ....133 12.4.19 PB_02 pad alternate function select register (PB_02_AFR) ....134 6 / 512 W7500 Datasheet Version1.0.0...
Page 7 12.4.53 PD_04 pad alternate function select register (PD_04_AFR) ....151 12.5 Register map ................152 13 External Interrupt (EXTI) ................155 13.1 Introduction ................155 13.2 Features ..................155 13.3 Functional description ..............155 7 / 512 W7500 Datasheet Version1.0.0...
Page 8 PC_02 external interrupt enable register (PC_02_EXTINT) ....175 13.4.36 PC_03 external interrupt enable register (PC_03_EXTINT) ....176 13.4.37 PC_04 external interrupt enable register (PC_04_EXTINT) ....176 13.4.38 PC_05 external interrupt enable register (PC_05_EXTINT) ....177 8 / 512 W7500 Datasheet Version1.0.0...
Page 9 PA_12 pad control register ............199 14.4.14 PA_13 pad control register ............199 14.4.15 PA_14 pad control register ............200 14.4.16 PA_15 pad control register ............201 14.4.17 PB_00 pad control register............201 14.4.18 PB_01 pad control register............202 9 / 512 W7500 Datasheet Version1.0.0...
Page 10 PD_02 pad control register ............225 14.4.52 PD_03 pad control register ............225 14.4.53 PD_04 pad control register ............226 14.5 Register map ................228 15 General-purpose I/Os(GPIO) ............... 232 15.1 Introduction ................232 15.2 Features ..................232 10 / 512 W7500 Datasheet Version1.0.0...
Page 11 Register map ................250 15.8 GPIOC Registers(Address Base: 0x4400_0000)........251 15.8.1 GPIOC Data Register(GPIOC_DATA) ..........251 15.8.2 GPIOC Output Latch Register(GPIOC_DATAOUT) ......251 15.8.3 GPIOC Enable Set Register(GPIOC_OUTENSET) ....... 251 15.8.4 GPIOC Enable Clear Register(GPIOC_OUTENCLR) ......252 11 / 512 W7500 Datasheet Version1.0.0...
Page 12 DMA cycle types ..............268 16.4 Registers (Base address : 0x4100_4000) ..........272 16.4.1 DMA status register (DMA_STATUS) ..........272 16.4.2 DMA configuration register (DMA_CFG) ........272 16.4.3 DMA control data base pointer register (DMA_CTRL_BASE_PTR) ..273 12 / 512 W7500 Datasheet Version1.0.0...
Page 13 Register map ................290 18 Pulse-Width Modulation (PWM) ..............291 18.1 Introduction ................291 18.2 Features ..................291 18.3 Functional description ..............292 18.3.1 Timer/Counter control ............292 18.3.2 Timer/Counter ..............292 18.3.3 PWM mode ................296 13 / 512 W7500 Datasheet Version1.0.0...
Page 14 18.6.11 Channel-1 PWM output Enable and External input Enable Register (PWMCH1PEEER) 316 18.6.12 Channel-1 Capture Mode Register (PWMCH1CMR) ......316 18.6.13 Channel-1 Capture Register (PWMCH1CR)........316 18.6.14 Channel-1 Periodic Mode Register (PWMCH1PDMR) ......317 14 / 512 W7500 Datasheet Version1.0.0...
Page 15 Channel-3 PWM output Enable and External input Enable Register (PWMCH3PEEER) 334 18.10.12 Channel-3 Capture Mode Register (PWMCH3CMR) ......334 18.10.13 Channel-3 Capture Register (PWMCH3CR)........334 18.10.14 Channel-3 Periodic Mode Register (PWMCH3PDMR) ......335 18.10.15 Channel-3 Dead Zone Enable Register (PWMCH3DZER) ..... 335 15 / 512 W7500 Datasheet Version1.0.0...
Page 16 Channel-5 Capture Mode Register (PWMCH5CMR) ......352 18.14.13 Channel-5 Capture Register (PWMCH5CR)........352 18.14.14 Channel-5 Periodic Mode Register (PWMCH5PDMR) ......353 18.14.15 Channel-5 Dead Zone Enable Register (PWMCH5DZER) ..... 353 18.14.16 Channel-5 Dead Zone Counter Register (PWMCH5DZCR) ....354 16 / 512 W7500 Datasheet Version1.0.0...
Page 17 Channel-7 Capture Register (PWMCH7CR)........370 18.18.14 Channel-7 Periodic Mode Register (PWMCH7PDMR) ......371 18.18.15 Channel-7 Dead Zone Enable Register (PWMCH7DZER) ..... 371 18.18.16 Channel-7 Dead Zone Counter Register (PWMCH7DZCR) ....372 18.19 Register map ................373 17 / 512 W7500 Datasheet Version1.0.0...
Page 18 Dual Timer 0 Clock Enable Register (Base address : 0x4000_1080) ....392 19.8.1 Timer0_0 Clock Enable Register (TIMCLKEN0_0) ......392 19.8.2 Timer0_1 Clock Enable Register (TIMCLKEN0_1) ......392 19.9 Register map ................393 19.10 Dual timer1_0 Registers (Base address : 0x4000_2000) ......394 18 / 512 W7500 Datasheet Version1.0.0...
Page 19 Watchdog timer Raw Interrupt Status Register (WDTMIS) ....409 20.4.7 Watchdog timer Lock Register(WDTLock) ........409 20.5 Register map ................411 21 Inter-integrated circuit interface (I2C) ............412 21.1 Introduction ................412 21.2 Features ..................412 19 / 512 W7500 Datasheet Version1.0.0...
Page 20 I2C1 Interrupt Status Register(I2C1_ISR) ........438 21.6.10 I2C1 Interrupt Status Clear Register(I2C1_ISCR) ......438 21.6.11 I2C1 Interrupt Status Mask Register(I2C1_ISMR) ......439 21.7 Register map ................441 22 UART(Universal Asynchronous Receive Transmit) ..........442 20 / 512 W7500 Datasheet Version1.0.0...
Page 21 UART1RIS (UART1 Raw Interrupt Status Register)......471 22.6.12 UART1MIS (UART1 Masked Interrupt Status Register) ....... 472 22.6.13 UART1ICR (UART1 Interrupt Clear Register) ........473 22.7 Register map ................475 23 Synchronous Serial Port (SSP) ..............476 23.1 Introduction ................476 21 / 512 W7500 Datasheet Version1.0.0...
Page 22 SSP1 Status register (SSP1SR) ........... 506 23.6.5 SSP1 Clock prescale register (SSP1CPSR) ........507 23.6.6 SSP1 Interrupt mask set or clear register (SSP1IMSC) ....... 507 23.6.7 SSP1 Raw interrupt status register (SSP1RIS) ......... 508 22 / 512 W7500 Datasheet Version1.0.0...
Page 23 SSP1 Masked interrupt status register, (SSP1MIS) ......508 23.6.9 SSP1 Interrupt clear register (SSP1ICR) ........509 23.6.10 SSP1 DMA control register, (SSP1DMACR) ........509 23.7 Register map ................511 Document History Information ............... 512 23 / 512 W7500 Datasheet Version1.0.0...
Page 24 List of table Table 1 W7500 interrupt assignments ............37 Table 2 W7500 sleep mode summary ............39 Table 3. Offset Address for Common Register ..........46 Table 4. Offset Address in Socket n Register Block (n = 0,…,7, where n is Socket number) ..................
Page 25 Table 40 UART1 register map and reset values ..........475 Table 41 DMA trigger points for the transmit and receive FIFOs......479 Table 42 SSP0 register map and reset values ..........503 Table 43 SSP1 register map and reset values ..........511 25 / 512 W7500 Datasheet Version1.0.0...
Page 26 List of figures Figure 1 W7500 System Architecture ............32 Figure 2 W7500 memory map ..............34 Figure 3 POR reset waveform ..............38 Figure 4 TOE block diagram ..............43 Figure 5. Register & Memory Organization ........... 45 Figure 6. operation of boot code .............. 84 Figure 7.
Page 27 Figure 71 Motorola SPI frame format, single and continuous transfers, with SPO=0 and SPH=1 ..................487 Figure 72 Motorola SPI frame format, single transfer, with SPO=1 and SPH=0..488 Figure 73. Motorola SPI frame format, continuous transfers, with SPO=1 and SPH=0 ....................489 27 / 512 W7500 Datasheet Version1.0.0...
Page 28 Figure 78. SPI master coupled to a PrimeCell SSP slave ........493 Figure 79. how to setting TI or Microwire mode flow chart ......494 Figure 80. how to setting SPI mode flow chart ..........495 28 / 512 W7500 Datasheet Version1.0.0...
Page 29: Documentation Conventions
Internet Group Management Protocol IPv4 Internet Protocol version 4 interrupt request NonMaskable Interrupt PADCON Pad Controller Phase-Locked Loop Physical Layer PPPoE Point-to-Point Protocol over Ethernet Power Of Reset Pulse Width Modulator Random Access Memory 29 / 512 W7500 Datasheet Version1.0.0...
Page 30 Random number generator Status Register Synchronous Serial Port SYSCFG System configuration controller TCPIPCore Offload Engine Transistor-Transistor Logic Transmission Control Protocol UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus User Datagram Protocol Wake On Lan Watchdog Timer 30 / 512 W7500 Datasheet Version1.0.0...
Page 31: Register Bit Conventions
Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Bit Accessibility Read/Write Read Only Read as 0 Read as 1 Write Only 31 / 512 W7500 Datasheet Version1.0.0...
Page 32: System And Memory Overview
WDOG UART2 PAD Controller Flash SPI0/SPI1 SPI x 2 Controller Alternate Function Controller I2C0/I2C1 Figure 1 W7500 System Architecture AHB-Lite BUS This bus connects the two masters (Cortex-M0 and uDMAC) and ten AHB slaves. 32 / 512 W7500 Datasheet Version1.0.0...
Page 33: Memory Organization
4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word‟s least significant byte and the highest numbered byte the most significant. 33 / 512 W7500 Datasheet Version1.0.0...
Page 34: 2.2.2 Memory Map
0x0002_0000 flash (128KB) 0x0000_1000 boot rom 0x0000_0000 0x0000_0000 BOOT PIN : LOW(0) BOOT PIN : HIGH(1) TEST PIN : LOW(0) TEST PIN : LOW(0) Normal operation mode Boot mode Figure 2 W7500 memory map 34 / 512 W7500 Datasheet Version1.0.0...
Page 35: System Configuration Controller (Syscfg)
00 : Flash memory mapped at 0x0000_0000 01 : Boot rom mapped at 0x0000_0000 10 : SRAM mapped at 0x0000_0000 11 : Noting mapped at 0x0000_0000 3.2.2 RESETOP register Address offset : 0x008 Reset value : 0x0000_0000 35 / 512 W7500 Datasheet Version1.0.0...
Page 36: 3.2.3 Rstinfo Register
[1] : if 1, Watchdog caused the reset. [2] : if 1, processor LOCKUP caused the reset. Interrupt and events Introduction W7500 contains interrupt service and event service as below  26ea interrupt request (IRQ) lines. One NonMaskable Interrupt (NMI).
Page 37: Interrupt Assignments
Interrupt assignments Table 1 describes the W7500 interrupt assignments. Table 1 W7500 interrupt assignments IRQ/NMI Device Description Address Watchdog Watchdog interrupt 0x0000_0008 IRQ[0] SSP0 SSP0 global interrupt 0x0000_0040 IRQ[1] SSP1 SSP1 global interrupt 0x0000_0044 IRQ[2] UART0 UART0 global interrupt 0x0000_0048...
Page 38: Event
Event W7500 is able to handle internal events in order to wake up the core(WFE). The wakeup event can be generated by When after DMA process finished  Power supply Introduction W7500 embeds a voltage regulator in order to supply the internal 1.5V digital power domain.
Page 39: Low-Power Modes
Low-power modes W7500 is in RUN mode after a system or power reset. There are two low power modes to save power when the CPU does not need to be kept running. These modes are useful for instances like when the CPU is waiting for an external interrupt. Please note that there is no power-off mode for W7500.
Page 40: System Tick Timer
An internal clock source control based on missing/meeting durations. The  COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 40 / 512 W7500 Datasheet Version1.0.0...
Page 41: Registers (Base : 0Xe000_E000)
The RELOAD value can be any value in the range 0x0000_0001 – 0x00FFFFFF. You can program a value of 0, but this has no effect because the SysTick exception request and COUNTFLAG are activated when count from 1 to 0. 41 / 512 W7500 Datasheet Version1.0.0...
Page 42: Systick Current Value Register (Syst_Cvr)
[30] SKEW - Reads as one. Calibration value for the 10ms inexact timing is not known because TENMS is not known. This can affect the suitability of SysTick as a software real time clock. [31] NOREF - Reads as one. Indicates that no separate reference clock is provided. 42 / 512 W7500 Datasheet Version1.0.0...
Page 43: Tcpipcore Offload Engine (Toe)
Internet connection to embedded systems. TOE enables users to have Internet connectivity in their applications by using the TCP/IP stack. WIZnet„s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE protocols. TOE embeds the 32Kbyte internal memory buffer for the Ethernet packet processing.
Page 44: Toe Memory Map
Regardless of the allocated size of each Socket TX/RX Buffer, it can be accessible within the 16 bits offset address range (From 0x0000 to 0xFFFF). Refer to „Chapter 7.4.3‟ for more information about 16KB TX/RX Memory organization and access method. 44 / 512 W7500 Datasheet Version1.0.0...
Page 45: Figure 5. Register & Memory Organization
0x4103_0000 Socket 0 RX Buffer Socket 0 Register 0x0000 0x4102_0000 Socket 0 TX Buffer 0xFFFF Reserved 0x4101_0000 Socket 0 Register 0x003A 0x0039 0x4100_0000 Common Register Common Register 0x0000 Figure 5. Register & Memory Organization 45 / 512 W7500 Datasheet Version1.0.0...
Page 46: Common Register Map
TOE supports 8 Sockets for communication channel. Each Socket is controlled by Socket n Register (n = 0,…,7 ,where n is socket number). <Table 2> defines the 16bits Offset Address of registers in Socket n Register Block. Refer to „Chapter 7.4.2‟ for more details about each register. 46 / 512 W7500 Datasheet Version1.0.0...
Page 47: Memory
16KB TX memory is initially allocated in 2KB size for each Socket TX Buffer Block (2KB X 8 = 16KB). The initial allocated 2KB size of Socket n TX Buffer can be re-allocated by using „Socket n TX Buffer Size Register (Sn_TXBUF_SIZE)‟. 47 / 512 W7500 Datasheet Version1.0.0...
Page 48 RX RD Pointer Register (Sn_RX_RD)‟ & „Socket n RX Write Pointer Register (Sn_RX_WR)‟. However, the 16bits Offset Address automatically converts into the physical address to be accessible in 16KB RX memory such as Figure 5. Refer to „Chapter 7.4.2‟ for Sn_RX_RD & Sn_RX_WR. 48 / 512 W7500 Datasheet Version1.0.0...
Page 49: Common Register (Base : 0X4100_0000)
[15:0] TCKCNT – Ticker counter register is used Tick counter of 100usec. for internal timer of TOE. The unit of tick is HCLK. Ex) HCLK is 20MHz, 0.0001sec./ (1sec./HCLK (=20000000)) = 2000(dec) = 0x7DC 7.5.3 IR (Interrupt Register) Address Offset : 0x2100 Reset value : 0x0000_0000 49 / 512 W7500 Datasheet Version1.0.0...
Page 50: Imr (Interrupt Mask Register)
IMR is „0‟, an interrupt will not be issued even if the corresponding bit of IR is „1‟. [4] Magic Packet 0: Disable Magic Packet Interrupt 1: Enable Magic Packet Interrupt [5] PPPoE Close Interrupt Mask 0: Disable PPPoE Close Interrupt 1: Enable PPPoE Close Interrupt 50 / 512 W7500 Datasheet Version1.0.0...
Page 51: Ircr (Interrupt Clear Register)
‘1’. Writing ‘0’ has no effect on the bit value. [4] Magic Packet Interrupt Clear [5] PPPoE Close Interrupt Clear [6] Destination unreachable Interrupt Clear [7] IP Conflict Interrupt Clear 7.5.6 SIR (Socket Interrupt Register) Address Offset : 0x2110 Reset value : 0x0000_0000 51 / 512 W7500 Datasheet Version1.0.0...
Page 52: Simr (Socket Interrupt Mask Register)
SIR is „1‟. [7:0] SIR - Socket n Interrupt Mast 0: Disable Socket n Interrupt 1: Enable Socket n Interrupt 7.5.8 MD (Mode Register) Address Offset : 0x2300 Reset value : 0x0000_0000 52 / 512 W7500 Datasheet Version1.0.0...
Page 53: Ptimer (Ppp Link Control Protocol Request Timer Register)
Reset value : 0x0000_0028 PTIME[7:0] [7:0] PTIME configures the time for sending LCP echo request. The unit of time is 25ms Ex) in case that PTIMER is 200, 200 * 25(ms) = 5000(ms) = 5 seconds 53 / 512 W7500 Datasheet Version1.0.0...
Page 54: Pmagicr (Ppp Link Control Protocol Magic Number Register)
LCP Magic number = 0x01010101 7.5.11 PHAR (Destination Hardware Address Register in PPPoE) Address Offset : 0x2408 Reset value : 0x0000_0000 PHAR[31:24] PHAR1[23:16] PHAR[15:8] PHAR[7:0] Address Offset : 0x240C Reset value : 0x0000_0000 PHAR[31:24] PHAR[23:16] 54 / 512 W7500 Datasheet Version1.0.0...
Page 55: Psidr (Session Id Register In Pppoe)
[15:0] PSID - should be written to the PPPoE sever session ID acquired in PPPoE connection process. 7.5.13 PMRUR (Maximum Receive Unit Register in PPPoE) Address Offset : 0x2414 Reset value : 0x0000_FFFF PMSS[15:0] 55 / 512 W7500 Datasheet Version1.0.0...
Page 56: Shar (Source Hardware Address Register)
Address Offset : 0x6004 Reset value : 0x0000_0000 SHA1[31:24] SHAR1[23:16] SHAR configures the source hardware address. Ex) In case of “00.08.DC.12.34.56” SHAR0[32:24] SHAR0[23:16] SHAR0 [15:8] SHAR0 [32:24] SHAR1 [32:24] SHAR2 [23:16] 0x00 0x08 0xDC 0x12 0x34 0x56 56 / 512 W7500 Datasheet Version1.0.0...
Page 57: Gar (Gateway Address)
Address Offset : 0x600C Reset value : 0x0000_0000 SUB[31:24] SUB[23:16] SUBR[15:8] SUBR[7:0] SUBR configures the subnet mask address. Ex) In case of “255.255.255.0” SUB[31:24] SUB[23:16] SUB[15:8] SUB[7:0] 255 (0xFF) 255 (0xFF) 255 (0xFF) 0 (0x00) 57 / 512 W7500 Datasheet Version1.0.0...
Page 58: Sipr (Source Ip Address Register)
GAR and SHAR. When LOCK is „ON‟, the protected registers are not able to access. In this case a value of 0x01ACCE55 is written to NCONFLR. When LOCK is „OFF‟, the protected registers are allowed to access. In this case any value except 0x01ACCE55 is written. 58 / 512 W7500 Datasheet Version1.0.0...
Page 59: Rtr (Retry Time Register)
Retry Time Register (Sn_RTR). Ex) When timeout-period is set as 400ms, RTR = (400ms / 1ms) X 10 = 4000(0x0FA0) RTR[15:8] 0x0F 7.5.20 RCR (Retry Counter Register) Address Offset : 0x6044 Reset value : 0x0000_0008 59 / 512 W7500 Datasheet Version1.0.0...
Page 60 „RCR+1‟ and there is no response to the TCP retransmission, the final timeout is occurred and Sn_IR(TIMEOUT) becomes „1‟. The time of final timeout (TCPTO) of TCP retransmission is as below. 60 / 512 W7500 Datasheet Version1.0.0...
Page 61: Uipr (Unreachable Ip Address Register)
UNREACH bit of IR becomes „1‟ and UIPR indicates the destination IP address. Ex) In case of “192.168.0.11” UIP[31:24] UIP[23:16] UIP[15:8] UIP[7:0] 192 (0xC0) 168 (0xA8) 0 (0x00) 11 (0x0E) 61 / 512 W7500 Datasheet Version1.0.0...
Page 62: Uportr (Unreachable Port Register)
Sn_MR (Socket n Mode Register) Address Offset : 0x0000 Reset value : 0x0000_0000 Sn_MR[7:0] Sn_MR configures the option or protocol type of Socket n. [3:0] These bits configures the protocol mode of Socket n as follows 62 / 512 W7500 Datasheet Version1.0.0...
Page 63 This bit is applied only during UDP mode(P[3:0] = „0010‟) and MULTI = „1‟. It configures the version for IGMP messages (Join/Leave/Report). Multicast Blocking in MACRAW mode 0 : disable Multicast Blocking 1 : enable Multicast Blocking 63 / 512 W7500 Datasheet Version1.0.0...
Page 64: Sn_Cr (Socket N Command Register)
Ethernet. If user wants to implement Hybrid TCP/IP stack, it is recommended that this bit is set as „1‟ for reducing host overhead to process the all received packets. 7.6.2 Sn_CR (Socket n Command Register) Address Offset : 0x0010 Reset value : 0x0000_0000 64 / 512 W7500 Datasheet Version1.0.0...
Page 65 CONNECT changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes „1‟. The connect-request fails in the following three cases. 1. When a ARP occurs (Sn_IR(3)=„1‟) because the destination hardware address is not acquired through the ARP-process. 65 / 512 W7500 Datasheet Version1.0.0...
Page 66 It checks the connection status by sending 1byte keep-alive packet. 0x22 SEND_KEEP If the peer cannot respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur. 66 / 512 W7500 Datasheet Version1.0.0...
Page 67: Sn_Ir (Socket N Interrupt Register)
[3] TIMEOUT Interrupt - This is issued when ARP or TCP occurs. [4] SENDOK Interrupt - This is issued when SEND command is completed 7.6.4 Sn_IMR (Socket n Interrupt Mask Register) Address Offset : 0x0024 Reset value: 0x0000_00FF Sn_IMR[4:0] 67 / 512 W7500 Datasheet Version1.0.0...
Page 68: Sn_Icr (Socket N Interrupt Clear Register)
Sn_ICR is used to clear interrupts. Each bit of Sn_IR can be cleared when the host writes „1‟ value to each bit of Sn_ICR corresponding to each bit of Sn_IR. [0] CONNECT Interrupt Clear [1] DISCONNECT Interrupt Clear [2] RECV Interrupt Mask [3] TIMEOUT Interrupt Mask [4] SENDOK Interrupt Mask 68 / 512 W7500 Datasheet Version1.0.0...
Page 69: Sn_Sr (Socket N Status Register)
SOCK_ESTABLISHED This indicates the status of the connection of Socket n. 0x17 It changes to SOCK_ESTABLISHED when the „TCP SERVER‟ processed the SYN packet from the „TCP CLIENT‟ during SOCK_LISTEN, or when the CONNECT command is successful. 69 / 512 W7500 Datasheet Version1.0.0...
Page 70 SOCK_SYNRECV request packet (SYN packet) from a peer. If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to SOCK_ESTABLISHED. If not, changes SOCK_CLOSED after timeout occurs (Sn_IR[TIMEOUT] = „1‟). 70 / 512 W7500 Datasheet Version1.0.0...
Page 71: Sn_Pnr (Socket N Protocol Number Register)
IANA (http://www.iana.org/assignments/protocol-numbers). Ex) Internet Control Message Protocol (ICMP) = 0x01, Internet Group Management Protocol = 0x02 7.6.8 Sn_TOSR (Socket n IP Type of Service Register) Address Offset : 0x0104 Reset value : 0x0000_0000 71 / 512 W7500 Datasheet Version1.0.0...
Page 72: Sn_Ttlr (Socket N Ttl Register)
Sn_TTL configures the TTL(Time To Live field in IP Header) of Socket n. It is set before OPEN command. For more the details, refer to http://www.iana.org/assignments/ip-parameters. 7.6.10 Sn_FRAGR (Socket n Fragment offset Register) Address Offset : 0x010C Reset value : 0x0000_4000 Sn_FRAG[15:0] [15:0] Sn_FRAG configures the FRAG(Fragment field in IP header) 72 / 512 W7500 Datasheet Version1.0.0...
Page 73: Sn_Mssr (Socket N Maximum Segment Register)
TCP is activated in Passive Mode. Ex) In case of Socket 0 MSS = 1460 (0x05B4), configure as below, 0x4101_0110 0x05B4 7.6.12 Sn_PORTR (Socket n Source Port Register) Address Offset : 0x0114 Reset value : 0x0000_0000 Sn_SPROT[15:0] 73 / 512 W7500 Datasheet Version1.0.0...
Page 74: Sn_Dhar (Socket N Destination Hardware Address Register)
Reset value : 0x0000_0000 Sn_DHAR1 [31:24] Sn_DHAR1 [23:16] Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or it indicates that it is acquired in ARP-process by CONNECT/SEND command. 74 / 512 W7500 Datasheet Version1.0.0...
Page 75: Sn_Dportr (Socket N Destination Port Number Register)
In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command. Ex) In case of Socket 0 Destination Port = 5000(0x1388), configure as below, 0x4101_0120 0x1388 7.6.15 Sn_DIPR (Socket n Destination IP address Register) Address Offset : 0x0124 Reset value : 0x0000_0000 75 / 512 W7500 Datasheet Version1.0.0...
Page 76: Sn_Katmr (Socket N Keep Alive Timer Register)
In case of 'Sn_KPALVTR > 0', WZTOE automatically transmits KA packet after time-period for checking the TCP connection (Auto- keepalive-process). In case of 'Sn_KPALVTR = 0', Auto-keep-alive-process will not operate, 76 / 512 W7500 Datasheet Version1.0.0...
Page 77: Sn_Rtr (Socket N Retry Time Register)
Ex) When timeout-period is set as 400ms, RTR = (400ms / 1ms) X 10 = 4000(0x0FA0) RTR[15:0] 0x0FA0 7.6.18 Sn_RCR (Socket n Retry Counter Register) Address Offset : 0x0188 Reset value : 0x0000_0000 77 / 512 W7500 Datasheet Version1.0.0...
Page 78: Sn_Txbuf_Size (Socket N Tx Buffer Size Register)
16KB TX Buffer and is assigned sequentially from Socket 0 to Socket 7. Socket n TX Buffer can be accessible with 16bits Offset Address ranged from 0x0000 to 0xFFFF regardless of the configured size. (Refer to Sn_TX_WR & Sn_TX_RD). Value (dec) 78 / 512 W7500 Datasheet Version1.0.0...
Page 79: Sn_Tx_Fsr (Socket N Tx Free Size Register)
If Sn_MR(P[3:0]) is TCP mode(„0001‟), it is automatically calculated as the difference between Sn_TX_WR and the internal ACK pointer which indicates the point of data is received already by the connected peer. Ex) In case of 2048(0x0800) in S0_TX_FSR, 0x4100_0204 0x0800 79 / 512 W7500 Datasheet Version1.0.0...
Page 80: Sn_Tx_Rd (Socket N Tx Read Pointer Register)
16bits value. 7.6.22 Sn_TX_WR (Socket n TX Write Pointer Register) Address Offset : 0x020C Reset value : 0x0000_0000 Sn_TXWP[15:0] 80 / 512 W7500 Datasheet Version1.0.0...
Page 81: Sn_Rxbuf_Size (Socket N Rx Buffer Size Register)
16KB RX Memory and is assigned sequentially from Socket 0 to Socket 7. Socket n RX Buffer Block can be accessible with the 16bits Offset Address ranged from 0x0000 to 0xFFFF regardless of the configured size. (Refer to Sn_RX_RD & Sn_RX_WR). Value (dec) Buffer size 16KB 81 / 512 W7500 Datasheet Version1.0.0...
Page 82: Sn_Rx_Rsr (Socket N Rx Received Size Register)
Therefore, it is recommended that you read all 16-bits twice or more until getting the same value. 7.6.25 Sn_RX_RD (Socket n RX Read Pointer Register) Address Offset : 0x0228 Reset value : 0x0000_0000 82 / 512 W7500 Datasheet Version1.0.0...
Page 83: Sn_Rx_Wr (Socket N Rx Write Pointer Register)
Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value. 83 / 512 W7500 Datasheet Version1.0.0...
Page 84: Booting Sequence
Ex) In case of 2048(0x0800) in S0_RX_WR, 0x4101_022C 0x0800 Booting Sequence W7500 has three different boot modes that can be selected through the BOOT pin and TEST pin as shown in Table 5. Table 5 operation of mode selection Mode...
Page 85: Embedded Flash Memory
0x0000 0300 ~ 0x0000 03FF Sector 3 Main Flash memory 0x0000 7000 ~ 0x0000 70FF Sector112 0x0000 7100 ~ 0x0000 71FF Sector113 Block 7 0x0000 7200 ~ 0x0000 72FF Sector114 0x0000 7300 ~ 0x0000 73FF Sector115 85 / 512 W7500 Datasheet Version1.0.0...
Page 86 BSADDR0 0x4100 503C ~ 0x4100 503F BSADDR1 The W7500 embedded Flash memory can be programmed using in-circuit programming or in- application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory using the SWD protocol or the boot loader to load the user application into the microcontroller.
Page 87: Read Operations
7. Wait until the RDY bit is 1 in the FSTATR register.( it is set when the programming operation has succeeded) 8. Set KEY in FKEYR0/R1 for clearing FACCR register. 9. Clear FEN and CTRL bits in the FACCR register 87 / 512 W7500 Datasheet Version1.0.0...
Page 88: Flash Erase Operations
5. Set SER bit in FACTRLR to 1. 6. Wait until the RDY bit is 1 in the FSTATR register. 7. Set KEY in FKEYR0/R1 for clearing FACCR register. 8. Clear FEN and CTRL bits in the FACCR register 88 / 512 W7500 Datasheet Version1.0.0...
Page 89: Figure 8. Flash Erase Operations
Mass Erase ( All main Flash memory erase + Data block erase ) To erase mass (Main Flash memory + Data block), Set MER bit in FACTRLR to 1. All other procedures are the same as the sector erase sequence. 89 / 512 W7500 Datasheet Version1.0.0...
Page 90: Flash Program Operation
Check the programmed value by Reading the programmed address Figure 9. main Flash memory programming sequence 1. Check that no main Flash memory operation is ongoing by checking the RDY bit in the FSTATR register. 90 / 512 W7500 Datasheet Version1.0.0...
Page 91: Memory Protection
 DWL0 : write protection to Data0 area in Data block.   DWL1 : write protection to Data1 area in Data block. CABWL : write protection to main Flash memory all block.  91 / 512 W7500 Datasheet Version1.0.0...
Page 92: Clock Reset Generator (Crg)
Clock Reset generator (CRG) 10.1 Introduction CRG is clock reset generator block for W7500 System. It provides every clock/reset for all other block include CPU and peripherals. CRG includes PLL and POR. 10.2 Features 10.2.1 Reset • Three types of reset – external reset, Power reset, system reset •...
Page 93: Functional Description
External crystal/ceramic resonator (8 to 24MHz external oscillator)  User external clock   Table 7 shows the two clock sources of external oscillator clock Table 7 External oscillator clock sources External clock Crystal/ 93 / 512 W7500 Datasheet Version1.0.0...
Page 94: 10.3.2 Rc Oscillator Clock
Each generated clock has own prescaler which can be selected individually by each prescale value register. FCLK, ADCCLK, SSPCLK, UARTCLK : 1/1, 1/2, 1/4, 1/8   TIMCLK0, TIMCLK1, PWMCLK0 – PWMCLK7, RTCCLK, WDOGCLK : 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 94 / 512 W7500 Datasheet Version1.0.0...
Page 95: Registers (Base Address : 0X4100_1000)
[0] PLLPD – PLL power down register This bit written by S/W to PLL power down or not 0 : power down 1 : normal operation 10.4.3 PLL frequency calculating register (PLL_FCR) Address offset : 0x014 Reset value : 0x0005_0200 95 / 512 W7500 Datasheet Version1.0.0...
Page 96: Pll Output Enable Register (Pll_Oer)
This bit written by S/W to control output enable of PLL 0 : Clock out is disable. VCO is working but FOUT is low only. 1 : Clock out is enable. 10.4.5 PLL bypass register (PLL_BPR) Address offset : 0x01c Reset value : 0x0000_0000 96 / 512 W7500 Datasheet Version1.0.0...
Page 97: Pll Input Clock Source Select Register (Pll_Ifsr)
1 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 10.4.7 FCLK source select register (FCLK_SSR) Address offset : 0x030 Reset value : 0x0000_0001 FCKSRC [1:0] FCKSRC – select register of FCLK clock source These bits are written by S/W to select 97 / 512 W7500 Datasheet Version1.0.0...
Page 98: Fclk Prescale Value Select Register (Fclk_Pvsr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 98 / 512 W7500 Datasheet Version1.0.0...
Page 99: Sspclk Prescale Value Select Register (Sspclk_Pvsr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 99 / 512 W7500 Datasheet Version1.0.0...
Page 100: Adcclk Prescale Value Select Register (Adcclk_Pvsr)
[0] T0CSS – TIMCLK0 clock source select register. These bits are written by S/W to select clock source 0 : disable clock 1 : FCLK 10.4.14 TIMER0CLK prescale value select register (TIMER0CLK_PVSR) Address offset : 0x074 Reset value : 0x0000_0000 100 / 512 W7500 Datasheet Version1.0.0...
Page 101: Timer1Clk Source Select Register (Timer1Clk_Ssr)
[0] T1CSS – TIMCLK1 clock source select register. These bits are written by S/W to select clock source 0 : disable clock 1 : FCLK 10.4.16 TIMER1CLK prescale value select register (TIMER1CLK_PVSR) Address offset : 0x084 Reset value : 0x0000_0000 101 / 512 W7500 Datasheet Version1.0.0...
Page 102: Pwm0Clk Source Select Register (Pwm0Clk_Ssr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 102 / 512 W7500 Datasheet Version1.0.0...
Page 103: Pwm0Clk Prescale Value Select Register (Pwm0Clk_Pvsr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 103 / 512 W7500 Datasheet Version1.0.0...
Page 104: Pwm1Clk Prescale Value Select Register (Pwm1Clk_Pvsr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 104 / 512 W7500 Datasheet Version1.0.0...
Page 105: Pwm2Clk Prescale Value Select Register (Pwm2Clk_Pvsr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 105 / 512 W7500 Datasheet Version1.0.0...
Page 106: Pwm3Clk Prescale Value Select Register (Pwm3Clk_Pvsr)
These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 10 : Internal 8MHz RC oscillator clock (RCLK) 11 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 106 / 512 W7500 Datasheet Version1.0.0...
Page 107: Pwm4Clk Prescale Value Select Register (Pwm4Clk_Pvsr)
Address offset : 0x100 Reset value : 0x0000_0001 P5CSS [1:0] P5CSS – PWMCLK5 clock source select register. These bits are written by S/W to select clock source 00 : disable clock 01 : PLL output clock (MCLK) 107 / 512 W7500 Datasheet Version1.0.0...
Page 108: Pwm5Clk Prescale Value Select Register (Pwm5Clk_Pvsr)
111 : 1/128 10.4.29 PWM6CLK source select register (PWM6CLK_SSR) Address offset : 0x110 Reset value : 0x0000_0001 P6CSS [1:0] P6CSS – PWMCLK6 clock source select register. These bits are written by S/W to select clock source 108 / 512 W7500 Datasheet Version1.0.0...
Page 109: Pwm6Clk Prescale Value Select Register (Pwm6Clk_Pvsr)
001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 10.4.31 PWM7CLK source select register (PWM7CLK_SSR) Address offset : 0x120 Reset value : 0x0000_0001 P7CSS 109 / 512 W7500 Datasheet Version1.0.0...
Page 110: Pwm7Clk Prescale Value Select Register (Pwm7Clk_Pvsr)
010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 10.4.33 WDOGCLK High Speed source select register (WDOGCLK_HS_SSR) Address offset : 0x140 Reset value : 0x0000_0001 110 / 512 W7500 Datasheet Version1.0.0...
Page 111: Wdogclk High Speed Prescale Value Select Register (Wdogclk_Hs_Pvsr)
001 : 1/2 010 : 1/4 011 : 1/8 100 : 1/16 101 : 1/32 110 : 1/64 111 : 1/128 10.4.35 UARTCLK source select register (UARTCLK_SSR) Address offset : 0x150 Reset value : 0x0000_0001 111 / 512 W7500 Datasheet Version1.0.0...
Page 112: Uartclk Prescale Value Select Register (Uartclk_Pvsr)
These bits are written by S/W to select 00 : 1/1 (bypass) 01 : 1/2 10 : 1/4 11 : 1/8 10.4.37 MIICLK enable control register (MIICLK_ECR) Address offset : 0x160 Reset value : 0x0000_0003 112 / 512 W7500 Datasheet Version1.0.0...
Page 113: Monitoring Clock Source Select Register (Monclk_Ssr)
00011 : External oscillator clock (OCLK, 8MHz ~ 24MHz) 00100 : ADCCLK 00101 : SSPCLK 00110 : TIMCLK0 00111 : TIMCLK1 01000 : PWMCLK0 01001 : PWMCLK1 01010 : PWMCLK2 01011 : PWMCLK3 01100 : PWMCLK4 113 / 512 W7500 Datasheet Version1.0.0...
Page 114 01101 : PWMCLK5 01110 : PWMCLK6 01111 : PWMCLK7 10000 : UARTCLK 10001 : MII_RCK 10010 : MII_TCK 10011 : RTCCLK 114 / 512 W7500 Datasheet Version1.0.0...
Page 115: Register Map
ADCCLK_SSR 0x060 reset value ADCCLK_PVSR 0x064 reset value TIMER0CLK_SSR 0x070 reset value TIMER0CLK_PVSR 0x074 reset value TIMER1CLK_SSR 0x080 reset value TIMER1CLK_PVSR 0x084 reset value PWM0CLK_SSR 0x0b0 reset value PWM0CLK_PVSR 0x0b4 reset value 115 / 512 W7500 Datasheet Version1.0.0...
Page 116 PWM7CLK_SSR 0x120 reset value PWM7CLK_PVSR 0x124 reset value WDOGCLK_HS_SSR 0x140 reset value WDOGCLK_HS_PVSR 0x144 reset value UARTCLK_SSR 0x150 reset value UARTCLK_PVSR 0x154 reset value MIICLK_ECR 0x160 reset value CLKMON_SEL MONCLK_SSR 0x170 reset value 116 / 512 W7500 Datasheet Version1.0.0...
Page 117: Random Number Generator (Rng)
Random value can be obtains by control start/stop by software. 11.3 Functional description Figure 11 shows the RNG block diagram. APB IF Controller (Registers) Polynomial Registers Shift Registers Seed Registers n = 32 Figure 11. Random Number Generator block diagram 117 / 512 W7500 Datasheet Version1.0.0...
Page 118: Operation Rng
Change seed value (if need) (RNG_SEED) Change polynomial value (if need) (RNG_POLY) Run RNG (RNG_RUN = 1) STOP RNG (RNG_RUN = 0) Read generated random number (RN) DONE Figure 12. Flow chart of RNG operation 118 / 512 W7500 Datasheet Version1.0.0...
Page 119: Registers (Base Address : 0X4000_7000)
[31:0] SEED – seed value of random number generator shift register These bits written by S/W to set seed value of RNG before start(run) RNG shift register 11.4.3 RNG clock select register (RNG_CLKSEL) Address offset : 0x008 Reset value : 0x0000_0000 119 / 512 W7500 Datasheet Version1.0.0...
Page 120: Rng Manual Mode Select Register (Rng_Mode)
0 : run/stop by PLL_LOCK signal (which is for power on random number) 1 : run/stop by RNG_RUN register (refer 1.4.1)R 11.4.5 RNG random number value register (RNG_RN) Address offset : 0x010 Reset value : 0x0000_0000 RN[31:16] 120 / 512 W7500 Datasheet Version1.0.0...
Page 121: Rng Polynomial Register (Rng_Poly)
Reset value : 0xE000_0202 POLY[31:16] POLY[15:0] [31:0] POLY – 32bit polynomial of random number generator These bits are written by S/W to modify the formula of random number generator Default polynomial: F(x) = x 121 / 512 W7500 Datasheet Version1.0.0...
Page 122: Register Map
Table 9 RNG register map and reset values Offset Register RNG_RUN 0x000 reset value SEED RNG_SEED 0x004 reset value RNG_CLKSEL 0x008 reset value RNG_MODE 0x00C reset value RNG_RN 0x010 reset value POLY RNG_POLY 0x014 reset value 122 / 512 W7500 Datasheet Version1.0.0...
Page 123: Alternate Function Controller (Afc)
GPIOA_10 U_RXD1 PWM7/CAP7 PA_11 U_CTS0 GPIOA_11 SSEL1 PA_12 U_RTS0 GPIOA_12 SCLK1 PA_13 U_TXD0 GPIOA_13 MISO1 PA_14 U_RXD0 GPIOA_14 MOSI1 PA_15 GPIOA_15 GPIOA_15 PB_00 SSEL1 GPIOB_0 U_CTS0 PB_01 SCLK1 GPIOB_1 U_RTS0 PB_02 MISO1 GPIOB_2 U_TXD0 123 / 512 W7500 Datasheet Version1.0.0...
Page 124 PC_12 AIN3 GPIOC_12 SSEL0 AIN3 PC_13 AIN2 GPIOC_13 SCLK0 AIN2 PC_14 AIN1 GPIOC_14 MISO0 AIN1 PC_15 AIN0 GPIOC_15 MOSI0 AIN0 PD_00 GPIOD_0 PD_01 RXDV GPIOD_1 PD_02 RXD0 GPIOD_2 PD_03 RXD1 GPIOD_3 PD_04 RXD2 GPIOD_4 124 / 512 W7500 Datasheet Version1.0.0...
Page 125: Registers (Base Address : 0X4100_2000)
Address offset : 0x004 Reset value : 0x0000_0000 PA01AF [1:0] PA01AF – PA_01 Pad function selection register. These bits are written by S/W. 00 : GPIOA_1 01 : GPIOA_1 10 : PWM7/CAP7 11 : None 125 / 512 W7500 Datasheet Version1.0.0...
Page 126: Pa_02 Pad Alternate Function Select Register (Pa_02_Afr)
Address offset : 0x00c Reset value : 0x0000_0000 PA03AF [1:0] PA03AF – PA_03 Pad function selection register. These bits are written by S/W. 00 : SWCLK 01 : GPIOA_3 10 : None 11 : PWM0/CAP0 126 / 512 W7500 Datasheet Version1.0.0...
Page 127: Pa_04 Pad Alternate Function Select Register (Pa_04_Afr)
Address offset : 0x014 Reset value : 0x0000_0000 PA05AF [1:0] PA05AF – PA_05 Pad function selection register. These bits are written by S/W. 00 : SSEL0 01 : GPIOA_5 10 : SCL1 11 : PWM2/CAP2 127 / 512 W7500 Datasheet Version1.0.0...
Page 128: Pa_06 Pad Alternate Function Select Register (Pa_06_Afr)
Address offset : 0x01c Reset value : 0x0000_0000 PA07AF [1:0] PA07AF – PA_07 Pad function selection register. These bits are written by S/W. 00 : MISO0 01 : GPIOA_7 10 : CTS1 11 : PWM4/CAP4 128 / 512 W7500 Datasheet Version1.0.0...
Page 129: Pa_08 Pad Alternate Function Select Register (Pa_08_Afr)
Address offset : 0x024 Reset value : 0x0000_0000 PA09AF [1:0] PA09AF – PA_09 Pad function selection register. These bits are written by S/W. 00 : SCL0 01 : GPIOA_9 10 : TXD1 11 : PWM6/CAP6 129 / 512 W7500 Datasheet Version1.0.0...
Page 130: Pa_10 Pad Alternate Function Select Register (Pa_10_Afr)
Address offset : 0x02c Reset value : 0x0000_0000 PA11AF [1:0] PA11AF – PA_11 Pad function selection register. These bits are written by S/W. 00 : CTS0 01 : GPIOA_11 10 : SSEL1 11 : None 130 / 512 W7500 Datasheet Version1.0.0...
Page 131: Pa_12 Pad Alternate Function Select Register (Pa_12_Afr)
Address offset : 0x034 Reset value : 0x0000_0000 PA13AF [1:0] PA13AF – PA_13 Pad function selection register. These bits are written by S/W. 00 : TXD0 01 : GPIOA_13 10 : MISO1 11 : None 131 / 512 W7500 Datasheet Version1.0.0...
Page 132: Pa_14 Pad Alternate Function Select Register (Pa_14_Afr)
Address offset : 0x03c Reset value : 0x0000_0000 PA15AF [1:0] PA15AF – PA_15 Pad function selection register. These bits are written by S/W. 00 : GPIOA_15 01 : GPIOA_15 10 : None 11 : None 132 / 512 W7500 Datasheet Version1.0.0...
Page 133: Pb_00 Pad Alternate Function Select Register (Pb_00_Afr)
Address offset : 0x044 Reset value : 0x0000_0000 PB01AF [1:0] PB01AF – PB_01 Pad function selection register. These bits are written by S/W. 00 : SCLK1 01 : GPIOB_1 10 : RTS0 11 : None 133 / 512 W7500 Datasheet Version1.0.0...
Page 134: Pb_02 Pad Alternate Function Select Register (Pb_02_Afr)
Address offset : 0x04c Reset value : 0x0000_0000 PB03AF [1:0] PB03AF – PB_03 Pad function selection register. These bits are written by S/W. 00 : MOSI1 01 : GPIOB_3 10 : RXD0 11 : None 134 / 512 W7500 Datasheet Version1.0.0...
Page 135: Pb_04 Pad Alternate Function Select Register (Pb_04_Afr)
Address offset : 0x054 Reset value : 0x0000_0000 PB05AF [1:0] PB05AF – PB_05 Pad function selection register. These bits are written by S/W. 00 : COL 01 : GPIOB_5 10 : None 11 : None 135 / 512 W7500 Datasheet Version1.0.0...
Page 136: Pb_06 Pad Alternate Function Select Register (Pb_06_Afr)
Address offset : 0x05c Reset value : 0x0000_0000 PB07AF [1:0] PB07AF – PB_07 Pad function selection register. These bits are written by S/W. 00 : RXCLK 01 : GPIOB_7 10 : None 11 : None 136 / 512 W7500 Datasheet Version1.0.0...
Page 137: Pb_08 Pad Alternate Function Select Register (Pb_08_Afr)
Address offset : 0x064 Reset value : 0x0000_0000 PB09AF [1:0] PB09AF – PB_09 Pad function selection register. These bits are written by S/W. 00 : TXCLK 01 : GPIOB_9 10 : None 11 : None 137 / 512 W7500 Datasheet Version1.0.0...
Page 138: Pb_10 Pad Alternate Function Select Register (Pb_10_Afr)
Address offset : 0x06c Reset value : 0x0000_0000 PB11AF [1:0] PB11AF – PB_11 Pad function selection register. These bits are written by S/W. 00 : TXD1 01 : GPIOB_11 10 : None 11 : None 138 / 512 W7500 Datasheet Version1.0.0...
Page 139: Pb_12 Pad Alternate Function Select Register (Pb_12_Afr)
Address offset : 0x074 Reset value : 0x0000_0000 PB13AF [1:0] PB13AF – PB_13 Pad function selection register. These bits are written by S/W. 00 : TXD3 01 : GPIOB_13 10 : None 11 : None 139 / 512 W7500 Datasheet Version1.0.0...
Page 140: Pb_14 Pad Alternate Function Select Register (Pb_14_Afr)
Address offset : 0x07c Reset value : 0x0000_0000 PB15AF [1:0] PB15AF – PB_15 Pad function selection register. These bits are written by S/W. 00 : MDC 01 : GPIOB_15 10 : None 11 : None 140 / 512 W7500 Datasheet Version1.0.0...
Page 141: Pc_00 Pad Alternate Function Select Register (Pc_00_Afr)
Address offset : 0x084 Reset value : 0x0000_0000 PC01AF [1:0] PC01AF – PC_01 Pad function selection register. These bits are written by S/W. 00 : RTS1 01 : GPIOC_1 10 : PWM1/CAP1 11 : None 141 / 512 W7500 Datasheet Version1.0.0...
Page 142: Pc_02 Pad Alternate Function Select Register (Pc_02_Afr)
Address offset : 0x08c Reset value : 0x0000_0000 PC03AF [1:0] PC03AF – PC_03 Pad function selection register. These bits are written by S/W. 00 : RXD1 01 : GPIOC_3 10 : PWM3/CAP3 11 : None 142 / 512 W7500 Datasheet Version1.0.0...
Page 143: Pc_04 Pad Alternate Function Select Register (Pc_04_Afr)
Address offset : 0x094 Reset value : 0x0000_0000 PC05AF [1:0] PC05AF – PC_05 Pad function selection register. These bits are written by S/W. 00 : SDA1 01 : GPIOC_5 10 : PWM5/CAP5 11 : None 143 / 512 W7500 Datasheet Version1.0.0...
Page 144: Pc_06 Pad Alternate Function Select Register (Pc_06_Afr)
Address offset : 0x09c Reset value : 0x0000_0000 PC07AF [1:0] PC07AF – PC_07 Pad function selection register. These bits are written by S/W. 00 : GPIOC_7 01 : GPIOC_7 10 : RXD2 11 : None 144 / 512 W7500 Datasheet Version1.0.0...
Page 145: Pc_08 Pad Alternate Function Select Register (Pc_08_Afr)
Address offset : 0x0a4 Reset value : 0x0000_0000 PC09AF [1:0] PC09AF – PC_09 Pad function selection register. These bits are written by S/W. 00 : PWM1/CAP1 01 : GPIOC_9 10 : SDA0 11 : ADC_IN6 145 / 512 W7500 Datasheet Version1.0.0...
Page 146: Pc_10 Pad Alternate Function Select Register (Pc_10_Afr)
Address offset : 0x0ac Reset value : 0x0000_0000 PC11AF [1:0] PC11AF – PC_11 Pad function selection register. These bits are written by S/W. 00 : RXD2 01 : GPIOC_11 10 : PWM3/CAP3 11 : ADC_IN4 146 / 512 W7500 Datasheet Version1.0.0...
Page 147: Pc_12 Pad Alternate Function Select Register (Pc_12_Afr)
Address offset : 0x0b4 Reset value : 0x0000_0000 PC13AF [1:0] PC13AF – PC_13 Pad function selection register. These bits are written by S/W. 00 : ADC_IN2 01 : GPIOC_13 10 : SCLK0 11 : ADC_IN2 147 / 512 W7500 Datasheet Version1.0.0...
Page 148: Pc_14 Pad Alternate Function Select Register (Pc_14_Afr)
Address offset : 0x0bc Reset value : 0x0000_0000 PC15AF [1:0] PC15AF – PC_15 Pad function selection register. These bits are written by S/W. 00 : ADC_IN0 01 : GPIOC_15 10 : MOSI0 11 : ADC_IN0 148 / 512 W7500 Datasheet Version1.0.0...
Page 149: Pd_00 Pad Alternate Function Select Register (Pd_00_Afr)
Address offset : 0x0c4 Reset value : 0x0000_0000 PD01AF [1:0] PD01AF – PD_01 Pad function selection register. These bits are written by S/W. 00 : RXDV 01 : GPIOD_1 10 : None 11 : None 149 / 512 W7500 Datasheet Version1.0.0...
Page 150: Pd_02 Pad Alternate Function Select Register (Pd_02_Afr)
Address offset : 0x0cc Reset value : 0x0000_0000 PD03AF [1:0] PD03AF – PD_03 Pad function selection register. These bits are written by S/W. 00 : RXD1 01 : GPIOD_3 10 : None 11 : None 150 / 512 W7500 Datasheet Version1.0.0...
Page 151: Pd_04 Pad Alternate Function Select Register (Pd_04_Afr)
Address offset : 0x0d0 Reset value : 0x0000_0000 PD04AF [1:0] PD04AF – PD_04 Pad function selection register. These bits are written by S/W. 00 : RXD2 01 : GPIOD_4 10 : None 11 : None 151 / 512 W7500 Datasheet Version1.0.0...
Page 152: Register Map
PA_10_AFR 0x028 reset value PA_11_AFR 0x02c reset value PA_12_AFR 0x030 reset value PA_13_AFR 0x034 reset value PA_14_AFR 0x038 reset value PA_15_AFR 0x03c reset value PB_00_AFR 0x040 reset value PB_01_AFR 0x044 reset value 152 / 512 W7500 Datasheet Version1.0.0...
Page 153 PB_14_AFR 0x078 reset value PB_15_AFR 0x07c reset value PC_00_AFR 0x080 reset value PC_01_AFR 0x084 reset value PC_02_AFR 0x088 reset value PC_03_AFR 0x08c reset value PC_04_AFR 0x090 reset value PC_05_AFR 0x094 reset value 153 / 512 W7500 Datasheet Version1.0.0...
Page 154 PC_13_AFR 0x0b4 reset value PC_14_AFR 0x0b8 reset value PC_15_AFR 0x0bc reset value PD_00_AFR 0x0c0 reset value PD_01_AFR 0x0c4 reset value PD_02_AFR 0x0c8 reset value PD_03_AFR 0x0cc reset value PD_04_AFR 0x0d0 reset value 154 / 512 W7500 Datasheet Version1.0.0...
Page 155: External Interrupt (Exti)
External Interrupt polarity register) External interrupt working as following expression: Each pad interrupt = Interrupt mask & (Interrupt polarity ^ Pad input)  EXTINT = any Each pad interrupt  Figure 13 shows the External Interrupt diagram. 155 / 512 W7500 Datasheet Version1.0.0...
Page 156: Figure 13. External Interrupt Diagram
PA_00_mask PA_00 PA_00_Polarity PA_15_mask PA_15 PA_15_Polarity PB_00_mask PB_00 PB_00_Polarity PB_15_mask EXTINT PB_15 PB_15_Polarity PC_00_mask PC_00 PC_00_Polarity PC_15_mask PC_15 PC_15_Polarity PD_00_mask PD_00 PD_00_Polarity PD_04_mask PD_04 PD_04_Polarity Figure 13. External Interrupt diagram 156 / 512 W7500 Datasheet Version1.0.0...
Page 157: Registers (Base Address : 0X4100_2000)
0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal [1] PA01IEN – External interrupt enable register of PA_01 PAD These bits are written by S/W. 157 / 512 W7500 Datasheet Version1.0.0...
Page 158: Pa_02 External Interrupt Enable Register (Pa_02_Extint)
Address offset : 0x20c Reset value : 0x0000_0000 PA03IEN PA03POL [0] PA03POL - External interrupt polarity selection register of PA_03 PAD These bits are written by S/W. 0 : interrupt occurs when pad detect rising edge signal 158 / 512 W7500 Datasheet Version1.0.0...
Page 159: Pa_04 External Interrupt Enable Register (Pa_04_Extint)
[1] PA04IEN – External interrupt enable register of PA_04 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.6 PA_05 external interrupt enable register (PA_05_EXTINT) Address offset : 0x214 Reset value : 0x0000_0000 159 / 512 W7500 Datasheet Version1.0.0...
Page 160: Pa_06 External Interrupt Enable Register (Pa_06_Extint)
[1] PA06IEN – External interrupt enable register of PA_06 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.8 PA_07 external interrupt enable register (PA_07_EXTINT) Address offset : 0x21c Reset value : 0x0000_0000 160 / 512 W7500 Datasheet Version1.0.0...
Page 161: Pa_08 External Interrupt Enable Register (Pa_08_Extint)
1 : interrupt occurs when pad detect falling edge signal [1] PA08IEN – External interrupt enable register of PA_08 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 161 / 512 W7500 Datasheet Version1.0.0...
Page 162: Pa_09 External Interrupt Enable Register (Pa_09_Extint)
0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal [1] PA10IEN – External interrupt enable register of PA_10 PAD These bits are written by S/W. 0 : external interrupt disable 162 / 512 W7500 Datasheet Version1.0.0...
Page 163: Pa_11 External Interrupt Enable Register (Pa_11_Extint)
[0] PA12POL - External interrupt polarity selection register of PA_12 PAD These bits are written by S/W. 0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal 163 / 512 W7500 Datasheet Version1.0.0...
Page 164: Pa_13 External Interrupt Enable Register (Pa_13_Extint)
0 : external interrupt disable 1 : external interrupt enable 13.4.15 PA_14 external interrupt enable register (PA_14_EXTINT) Address offset : 0x238 Reset value : 0x0000_0000 PA14TIEN PA14POL [0] PA14POL - External interrupt polarity selection register of PA_14 PAD 164 / 512 W7500 Datasheet Version1.0.0...
Page 165: Pa_15 External Interrupt Enable Register (Pa_15_Extint)
[1] PA15IEN – External interrupt enable register of PA_15 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.17 PB_00 external interrupt enable register (PB_00_EXTINT) Address offset : 0x240 Reset value : 0x0000_0000 165 / 512 W7500 Datasheet Version1.0.0...
Page 166: Pb_01 External Interrupt Enable Register (Pb_01_Extint)
[1] PB01IEN – External interrupt enable register of PB_01 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.19 PB_02 external interrupt enable register (PB_02_EXTINT) Address offset : 0x248 Reset value : 0x0000_0000 166 / 512 W7500 Datasheet Version1.0.0...
Page 167: Pb_03 External Interrupt Enable Register (Pb_03_Extint)
1 : interrupt occurs when pad detect falling edge signal [1] PB03IEN – External interrupt enable register of PB_03 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 167 / 512 W7500 Datasheet Version1.0.0...
Page 168: Pb_04 External Interrupt Enable Register (Pb_04_Extint)
0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal [1] PB05IEN – External interrupt enable register of PB_05 PAD These bits are written by S/W. 0 : external interrupt disable 168 / 512 W7500 Datasheet Version1.0.0...
Page 169: Pb_06 External Interrupt Enable Register (Pb_06_Extint)
[0] PB07POL - External interrupt polarity selection register of PB_07 PAD These bits are written by S/W. 0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal 169 / 512 W7500 Datasheet Version1.0.0...
Page 170: Pb_08 External Interrupt Enable Register (Pb_08_Extint)
0 : external interrupt disable 1 : external interrupt enable 13.4.26 PB_09 external interrupt enable register (PB_09_EXTINT) Address offset : 0x264 Reset value : 0x0000_0000 PB09IEN PB09POL [0] PB09POL - External interrupt polarity selection register of PB_09 PAD 170 / 512 W7500 Datasheet Version1.0.0...
Page 171: Pb_10 External Interrupt Enable Register (Pb_10_Extint)
[1] PB10IEN – External interrupt enable register of PB_10 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.28 PB_11 external interrupt enable register (PB_11_EXTINT) Address offset : 0x26c Reset value : 0x0000_0000 171 / 512 W7500 Datasheet Version1.0.0...
Page 172: Pb_12 External Interrupt Enable Register (Pb_12_Extint)
[1] PB12IEN – External interrupt enable register of PB_12 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.30 PB_13 external interrupt enable register (PB_13_EXTINT) Address offset : 0x274 Reset value : 0x0000_0000 172 / 512 W7500 Datasheet Version1.0.0...
Page 173: Pb_14 External Interrupt Enable Register (Pb_14_Extint)
1 : interrupt occurs when pad detect falling edge signal [1] PB14IEN – External interrupt enable register of PB_14 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 173 / 512 W7500 Datasheet Version1.0.0...
Page 174: Pb_15 External Interrupt Enable Register (Pb_15_Extint)
0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal [1] PC00IEN – External interrupt enable register of PC_00 PAD These bits are written by S/W. 0 : external interrupt disable 174 / 512 W7500 Datasheet Version1.0.0...
Page 175: Pc_01 External Interrupt Enable Register (Pc_01_Extint)
[0] PC02POL - External interrupt polarity selection register of PC_02 PAD These bits are written by S/W. 0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal 175 / 512 W7500 Datasheet Version1.0.0...
Page 176: Pc_03 External Interrupt Enable Register (Pc_03_Extint)
0 : external interrupt disable 1 : external interrupt enable 13.4.37 PC_04 external interrupt enable register (PC_04_EXTINT) Address offset : 0x290 Reset value : 0x0000_0000 PC04IEN PC04POL [0] PC04POL - External interrupt polarity selection register of PC_04 PAD 176 / 512 W7500 Datasheet Version1.0.0...
Page 177: Pc_05 External Interrupt Enable Register (Pc_05_Extint)
[1] PC05IEN – External interrupt enable register of PC_05 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.39 PC_06 external interrupt enable register (PC_06_EXTINT) Address offset : 0x298 Reset value : 0x0000_0000 177 / 512 W7500 Datasheet Version1.0.0...
Page 178: Pc_07 External Interrupt Enable Register (Pc_07_Extint)
[1] PC07IEN – External interrupt enable register of PC_07 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.41 PC_08 external interrupt enable register (PC_08_EXTINT) Address offset : 0x2a0 Reset value : 0x0000_0000 178 / 512 W7500 Datasheet Version1.0.0...
Page 179: Pc_09 External Interrupt Enable Register (Pc_09_Extint)
1 : interrupt occurs when pad detect falling edge signal [1] PC09IEN – External interrupt enable register of PC_09 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 179 / 512 W7500 Datasheet Version1.0.0...
Page 180: Pc_10 External Interrupt Enable Register (Pc_10_Extint)
0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal [1] PC11IEN – External interrupt enable register of PC_11 PAD These bits are written by S/W. 0 : external interrupt disable 180 / 512 W7500 Datasheet Version1.0.0...
Page 181: Pc_12 External Interrupt Enable Register (Pc_12_Extint)
[0] PC13POL - External interrupt polarity selection register of PC_13 PAD These bits are written by S/W. 0 : interrupt occurs when pad detect rising edge signal 1 : interrupt occurs when pad detect falling edge signal 181 / 512 W7500 Datasheet Version1.0.0...
Page 182: Pc_14 External Interrupt Enable Register (Pc_14_Extint)
0 : external interrupt disable 1 : external interrupt enable 13.4.48 PC_15 external interrupt enable register (PC_15_EXTINT) Address offset : 0x2bc Reset value : 0x0000_0000 PC15IEN PC15POL [0] PC15POL - External interrupt polarity selection register of PC_15 PAD 182 / 512 W7500 Datasheet Version1.0.0...
Page 183: Pd_00 External Interrupt Enable Register (Pd_00_Extint)
[1] PD00IEN – External interrupt enable register of PD_00 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.50 PD_01 external interrupt enable register (PD_01_EXTINT) Address offset : 0x2c4 Reset value : 0x0000_0000 183 / 512 W7500 Datasheet Version1.0.0...
Page 184: Pd_02 External Interrupt Enable Register (Pd_02_Extint)
[1] PD02IEN – External interrupt enable register of PD_02 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 13.4.52 PD_03 external interrupt enable register (PD_03_EXTINT) Address offset : 0x2cc Reset value : 0x0000_0000 184 / 512 W7500 Datasheet Version1.0.0...
Page 185: Pd_04 External Interrupt Enable Register (Pd_04_Extint)
1 : interrupt occurs when pad detect falling edge signal [1] PD04IEN – External interrupt enable register of PD_04 PAD These bits are written by S/W. 0 : external interrupt disable 1 : external interrupt enable 185 / 512 W7500 Datasheet Version1.0.0...
Page 186: Register Map
PA_10_EXTINT 0x228 reset value PA_11_EXTINT 0x22c reset value PA_12_EXTINT 0x230 reset value PA_13_EXTINT 0x234 reset value PA_14_EXTINT 0x238 reset value PA_15_EXTINT 0x23c reset value PB_00_EXTINT 0x240 reset value PB_01_EXTINT 0x244 reset value 186 / 512 W7500 Datasheet Version1.0.0...
Page 187 PB_13_EXTINT 0x274 reset value PB_14_EXTINT 0x278 reset value PB_15_EXTINT 0x27c reset value PC_00_EXTINT 0x280 reset value PC_01_EXTINT 0x284 reset value PC_02_EXTINT 0x288 reset value PC_03_EXTINT 0x28c reset value PC_04_EXTINT 0x290 reset value 187 / 512 W7500 Datasheet Version1.0.0...
Page 188 PC_13_EXTINT 0x2b4 reset value PC_14_EXTINT 0x2b8 reset value PC_15_EXTINT 0x2bc reset value PD_00_EXTINT 0x2c0 reset value PD_01_EXTINT 0x2c4 reset value PD_02_EXTINT 0x2c8 reset value PD_03_EXTINT 0x2cc reset value PD_04_EXTINT 0x2d0 reset value 188 / 512 W7500 Datasheet Version1.0.0...
Page 189: Pad Controller (Padcon)
Functional description Figure 14 shows the function schematic of digital I/O pad of W7500. Figure 14. function schematic of digital I/O pad Figure 15 shows the function schematic of digital/analog mux IO pad of W7500 189 / 512 W7500 Datasheet Version1.0.0...
Page 190: Registers (Base Address : 0X4100_3000)
User can set pad condition with IE, CS, PU/PD, DS by register. And pads are can be controlled individually. 14.4 Registers (Base address : 0x4100_3000) 14.4.1 PA_00 pad control register Address offset : 0x000 Reset value : 0x0000_0030 PA00_CS PA00_IE PA00_DS PA00_PUPD 190 / 512 W7500 Datasheet Version1.0.0...
Page 191: 14.4.2 Pa_01 Pad Control Register
[2] PA01_DS – Driving strength selection register of Pad PA_01 0 : Low driving strength 1 : High driving strength [5] PA01_IE : Input buffer enable selection register of Pad PA_01 0 : Input buffer disable 191 / 512 W7500 Datasheet Version1.0.0...
Page 192: 14.4.3 Pa_02 Pad Control Register
[6] PA02_CS – CMOS input or Summit trigger input selection register of Pad PA_02 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.4 PA_03 pad control register Address offset : 0x00c Reset value : 0x0000_0030 192 / 512 W7500 Datasheet Version1.0.0...
Page 193: 14.4.5 Pa_04 Pad Control Register
These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PA04_DS – Driving strength selection register of Pad PA_04 0 : Low driving strength 1 : High driving strength 193 / 512 W7500 Datasheet Version1.0.0...
Page 194: 14.4.6 Pa_05 Pad Control Register
[6] PA05_CS – CMOS input or Summit trigger input selection register of Pad PA_05 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.7 PA_06 pad control register Address offset : 0x018 Reset value : 0x0000_0030 194 / 512 W7500 Datasheet Version1.0.0...
Page 195: 14.4.8 Pa_07 Pad Control Register
[1:0] PA07_PUPD – Pull-up, Pull-down selection register of Pad PA_07 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PA07_DS – Driving strength selection register of Pad PA_07 195 / 512 W7500 Datasheet Version1.0.0...
Page 196: 14.4.9 Pa_08 Pad Control Register
[6] PA08_CS – CMOS input or Summit trigger input selection register of Pad PA_08 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.10 PA_09 pad control register Address offset : 0x024 Reset value : 0x0000_0030 196 / 512 W7500 Datasheet Version1.0.0...
Page 197: Pa_10 Pad Control Register
Address offset : 0x028 Reset value : 0x0000_0030 PA10_CS PA10_IE PA10_DS PA10_PUPD [1:0] PA10_PUPD – Pull-up, Pull-down selection register of Pad PA_10 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 197 / 512 W7500 Datasheet Version1.0.0...
Page 198: Pa_11 Pad Control Register
0 : Input buffer disable 1 : Input buffer enable [6] PA11_CS – CMOS input or Summit trigger input selection register of Pad PA_11 0 : CMOS input buffer 1 : Summit trigger input buffer 198 / 512 W7500 Datasheet Version1.0.0...
Page 199: Pa_12 Pad Control Register
[6] PA12_CS – CMOS input or Summit trigger input selection register of Pad PA_12 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.14 PA_13 pad control register Address offset : 0x034 Reset value : 0x0000_0030 PA13_CS PA13_IE PA13_DS PA13_PUPD 199 / 512 W7500 Datasheet Version1.0.0...
Page 200: Pa_14 Pad Control Register
[2] PA14_DS – Driving strength selection register of Pad PA_14 0 : Low driving strength 1 : High driving strength [5] PA14_IE : Input buffer enable selection register of Pad PA_14 0 : Input buffer disable 1 : Input buffer enable 200 / 512 W7500 Datasheet Version1.0.0...
Page 201: Pa_15 Pad Control Register
[6] PA15_CS – CMOS input or Summit trigger input selection register of Pad PA_15 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.17 PB_00 pad control register Address offset : 0x040 Reset value : 0x0000_0030 201 / 512 W7500 Datasheet Version1.0.0...
Page 202: Pb_01 Pad Control Register
These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PB01_DS – Driving strength selection register of Pad PB_01 0 : Low driving strength 1 : High driving strength 202 / 512 W7500 Datasheet Version1.0.0...
Page 203: Pb_02 Pad Control Register
[6] PB02_CS – CMOS input or Summit trigger input selection register of Pad PB_02 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.20 PB_03 pad control register Address offset : 0x04c Reset value : 0x0000_0030 203 / 512 W7500 Datasheet Version1.0.0...
Page 204: Pb_04 Pad Control Register
[1:0] PB04_PUPD – Pull-up, Pull-down selection register of Pad PB_04 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PB04_DS – Driving strength selection register of Pad PB_04 204 / 512 W7500 Datasheet Version1.0.0...
Page 205: Pb_05 Pad Control Register
[6] PB05_CS – CMOS input or Summit trigger input selection register of Pad PB_05 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.23 PB_06 pad control register Address offset : 0x058 Reset value : 0x0000_0030 205 / 512 W7500 Datasheet Version1.0.0...
Page 206: Pb_07 Pad Control Register
Address offset : 0x05c Reset value : 0x0000_0030 PB07_CS PB07_IE PB07_DS PB07_PUPD [1:0] PB07_PUPD – Pull-up, Pull-down selection register of Pad PB_07 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 206 / 512 W7500 Datasheet Version1.0.0...
Page 207: Pb_08 Pad Control Register
0 : Input buffer disable 1 : Input buffer enable [6] PB08_CS – CMOS input or Summit trigger input selection register of Pad PB_08 0 : CMOS input buffer 1 : Summit trigger input buffer 207 / 512 W7500 Datasheet Version1.0.0...
Page 208: Pb_09 Pad Control Register
1 : Summit trigger input buffer 14.4.27 PB_10 pad control register Address offset : 0x068 Reset value : 0x0000_0030 PB10_CS PB10_IE PB10_DS PB10_PUPD [1:0] PB10_PUPD – Pull-up, Pull-down selection register of Pad PB_10 These bits are written by S/W. 208 / 512 W7500 Datasheet Version1.0.0...
Page 209: Pb_11 Pad Control Register
[5] PB11_IE : Input buffer enable selection register of Pad PB_11 0 : Input buffer disable 1 : Input buffer enable [6] PB11_CS – CMOS input or Summit trigger input selection register of Pad PB_11 0 : CMOS input buffer 209 / 512 W7500 Datasheet Version1.0.0...
Page 210: Pb_12 Pad Control Register
[6] PB12_CS – CMOS input or Summit trigger input selection register of Pad PB_12 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.30 PB_13 pad control register Address offset : 0x074 Reset value : 0x0000_0030 PB13_CS PB13_IE PB13_DS PB13_PUPD 210 / 512 W7500 Datasheet Version1.0.0...
Page 211: Pb_14 Pad Control Register
[2] PB14_DS – Driving strength selection register of Pad PB_14 0 : Low driving strength 1 : High driving strength [5] PB14_IE : Input buffer enable selection register of Pad PB_14 0 : Input buffer disable 211 / 512 W7500 Datasheet Version1.0.0...
Page 212: Pb_15 Pad Control Register
[6] PB15_CS – CMOS input or Summit trigger input selection register of Pad PB_15 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.33 PC_00 pad control register Address offset : 0x080 Reset value : 0x0000_0030 212 / 512 W7500 Datasheet Version1.0.0...
Page 213: Pc_01 Pad Control Register
These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PC01_DS – Driving strength selection register of Pad PC_01 0 : Low driving strength 1 : High driving strength 213 / 512 W7500 Datasheet Version1.0.0...
Page 214: Pc_02 Pad Control Register
[6] PC02_CS – CMOS input or Summit trigger input selection register of Pad PC_02 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.36 PC_03 pad control register Address offset : 0x08C Reset value : 0x0000_0030 214 / 512 W7500 Datasheet Version1.0.0...
Page 215: Pc_04 Pad Control Register
[1:0] PC04_PUPD – Pull-up, Pull-down selection register of Pad PC_04 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PC04_DS – Driving strength selection register of Pad PC_04 215 / 512 W7500 Datasheet Version1.0.0...
Page 216: Pc_05 Pad Control Register
[6] PC05_CS – CMOS input or Summit trigger input selection register of Pad PC_05 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.39 PC_06 pad control register Address offset : 0x098 Reset value : 0x0000_0030 216 / 512 W7500 Datasheet Version1.0.0...
Page 217: Pc_07 Pad Control Register
Address offset : 0x09C Reset value : 0x0000_0030 PC07_CS PC07_IE PC07_DS PC07_PUPD [1:0] PC07_PUPD – Pull-up, Pull-down selection register of Pad PC_07 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 217 / 512 W7500 Datasheet Version1.0.0...
Page 218: Pc_08 Pad Control Register
0 : Input buffer disable 1 : Input buffer enable [6] PC08_CS – CMOS input or Summit trigger input selection register of Pad PC_08 0 : CMOS input buffer 1 : Summit trigger input buffer 218 / 512 W7500 Datasheet Version1.0.0...
Page 219: Pc_09 Pad Control Register
1 : Summit trigger input buffer 14.4.43 PC_10 pad control register Address offset : 0x0A8 Reset value : 0x0000_0030 PC10_CS PC10_IE PC10_DS PC10_PUPD [1:0] PC10_PUPD – Pull-up, Pull-down selection register of Pad PC_10 These bits are written by S/W. 219 / 512 W7500 Datasheet Version1.0.0...
Page 220: Pc_11 Pad Control Register
[5] PC11_IE : Input buffer enable selection register of Pad PC_11 0 : Input buffer disable 1 : Input buffer enable [6] PC11_CS – CMOS input or Summit trigger input selection register of Pad PC_11 0 : CMOS input buffer 220 / 512 W7500 Datasheet Version1.0.0...
Page 221: Pc_12 Pad Control Register
[6] PC12_CS – CMOS input or Summit trigger input selection register of Pad PC_12 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.46 PC_13 pad control register Address offset : 0x0B4 Reset value : 0x0000_0030 PC13_CS PC13_IE PC13_DS PC13_PUPD 221 / 512 W7500 Datasheet Version1.0.0...
Page 222: Pc_14 Pad Control Register
[2] PC14_DS – Driving strength selection register of Pad PC_14 0 : Low driving strength 1 : High driving strength [5] PC14_IE : Input buffer enable selection register of Pad PC_14 0 : Input buffer disable 222 / 512 W7500 Datasheet Version1.0.0...
Page 223: Pc_15 Pad Control Register
[6] PC15_CS – CMOS input or Summit trigger input selection register of Pad PC_15 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.49 PD_00 pad control register Address offset : 0x0C0 Reset value : 0x0000_0030 223 / 512 W7500 Datasheet Version1.0.0...
Page 224: Pd_01 Pad Control Register
These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PD01_DS – Driving strength selection register of Pad PD_01 0 : Low driving strength 1 : High driving strength 224 / 512 W7500 Datasheet Version1.0.0...
Page 225: Pd_02 Pad Control Register
[6] PD02_CS – CMOS input or Summit trigger input selection register of Pad PD_02 0 : CMOS input buffer 1 : Summit trigger input buffer 14.4.52 PD_03 pad control register Address offset : 0x0CC Reset value : 0x0000_0030 225 / 512 W7500 Datasheet Version1.0.0...
Page 226: Pd_04 Pad Control Register
[1:0] PD04_PUPD – Pull-up, Pull-down selection register of Pad PD_04 These bits are written by S/W. 00 : Neither 01 : pull-down 10 : pull-up 11 : Neither [2] PD04_DS – Driving strength selection register of Pad PD_04 226 / 512 W7500 Datasheet Version1.0.0...
Page 227 0 : Input buffer disable 1 : Input buffer enable [6] PD04_CS – CMOS input or Summit trigger input selection register of Pad PD_04 0 : CMOS input buffer 1 : Summit trigger input buffer 227 / 512 W7500 Datasheet Version1.0.0...
Page 228: Register Map
PCR_PA06 0x018 reset value PCR_PA07 0x01c reset value PCR_PA08 0x020 reset value PCR_PA09 0x024 reset value PCR_PA10 0x028 reset value PCR_PA11 0x02c reset value PCR_PA12 0x030 reset value PCR_PA13 0x034 reset value 228 / 512 W7500 Datasheet Version1.0.0...
Page 229 PCR_PB05 0x054 reset value PCR_PB06 0x058 reset value PCR_PB07 0x05c reset value PCR_PB08 0x060 reset value PCR_PB09 0x064 reset value PCR_PB10 0x068 reset value PCR_PB11 0x06c reset value PCR_PB12 0x070 reset value 229 / 512 W7500 Datasheet Version1.0.0...
Page 230 PCR_PC04 0x090 reset value PCR_PC05 0x094 reset value PCR_PC06 0x098 reset value PCR_PC07 0x09c reset value PCR_PC08 0x0a0 reset value PCR_PC09 0x0a4 reset value PCR_PC10 0x0a8 reset value PCR_PC11 0x0ac reset value 230 / 512 W7500 Datasheet Version1.0.0...
Page 231 PCR_PC13 0x0b4 reset value PCR_PC14 0x0b8 reset value PCR_PC15 0x0bc reset value PCR_PD00 0x0c0 reset value PCR_PD01 0x0c4 reset value PCR_PD02 0x0c8 reset value PCR_PD03 0x0cc reset value PCR_PD04 0x0d0 reset value 231 / 512 W7500 Datasheet Version1.0.0...
Page 232: General-Purpose I/Os(Gpio)
Block GPIOINT[15:0] Pin Mux Alternate function signals Figure 16. GPIO block diagram Figure 17 shows the operation sequences available for the GPIO. The pad alternate function is using the pad alternate function select register. 232 / 512 W7500 Datasheet Version1.0.0...
Page 233: Masked Access
For example, to set bits[1:0] to 1 and clear bits[7:6] in a single operation, users can carry out the write to the lower byte mask access address space. The required bit mask is 0xC3, and users can write the operation as MASKLOWBYTE[0xC3] = 0x03. Refer to Figure 18 below. 233 / 512 W7500 Datasheet Version1.0.0...
Page 234: Figure 18. Mask Lowbyte Access
Upper byte masked access register bit mask : 'b1001_1000(0x98) set bit[12:11] to 0 0x0800 clear bit[15] to 1 DATAOUT = 0x322B lower byte masked access register 0x0400 DATA /Control register 0x0000 Figure 19 MASK HIGHBYTE access 234 / 512 W7500 Datasheet Version1.0.0...
Page 235: Gpioa Registers(Address Base: 0X4200_0000)
DAO4 DAO3 DAO2 DAO1 DAO0 [15:0] DAOy(y = 0..15) READ as : Port out data bit WRITE as : WRITE to GPIOA_DATAOUT register 15.4.3 GPIOA Enable Set Register(GPIOA_OUTENSET) Address offset: 0x0010 Reset value: 0x0000 235 / 512 W7500 Datasheet Version1.0.0...
Page 236: Gpioa Enable Clear Register(Gpioa_Outenclr)
„1‟ is clears the output enable bit READ as : „0‟ is indicates the signal direction as input „1‟ is indicates the signal direction as output 15.4.5 GPIOA Interrupt Enable Set Register(GPIOA_ INTENSET) Address offset: 0x0020 Reset value: 0x0000 236 / 512 W7500 Datasheet Version1.0.0...
Page 237: Gpioa Interrupt Enable Clear Register(Gpioa_ Intenclr)
„1‟ is clears the interrupt enable bit READ as : „0‟ is indicates the interrupt disable „1‟ is indicates the interrupt enable 15.4.7 GPIOA Interrupt Type Set Register(GPIOA_ INTTYPESET) Address offset: 0x0028 Reset value: 0x---- 237 / 512 W7500 Datasheet Version1.0.0...
Page 238: Gpioa Interrupt Type Clear Register(Gpioa_ Inttypeclr)
„1‟ is clears the interrupt type bit READ as : „0‟ is indicates for LOW or HIGH level „1‟ is indicates for falling edge or rising edge 15.4.9 GPIOA Interrupt Polarity Set Register(GPIOA_ INTPOLSET) Address offset: 0x0030 Reset value: 0x---- 238 / 512 W7500 Datasheet Version1.0.0...
Page 239: Gpioa Interrupt Polarity Clear Register(Gpioa_ Intpolclr)
„1‟ is clears the interrupt polarity bit READ as : „0‟ is indicates for LOW level or falling edge „1‟ is indicates for HIGH level or rising edge 15.4.11 GPIOA Interrupt Status/Interrupt Clear Register(GPIOA_ INTSTATUS/ INTCLEAR) Address offset: 0x0038 239 / 512 W7500 Datasheet Version1.0.0...
Page 240: Gpioa Lower Byte Masked Access Register(Gpioa_ Lb_Masked)
[15:8] Not used [7:0] Data for lower byte access, with bits[9:2] of address value used as enable bit mask for each bit 15.4.13 GPIOA Upper Byte Masked Access Register(GPIOA_ UB_MASKED) Address offset: 0x0800-0x0FC Reset value: 0x---- 240 / 512 W7500 Datasheet Version1.0.0...
Page 241 Higher eight bits masked access [15:8] Data for higher byte access, with bits[9:2] of address value used as enable bit mask for each bit [7:0] Not used 241 / 512 W7500 Datasheet Version1.0.0...
Page 242: Register Map
0x34 GPIOA INTSTATUS/ Interrupt status register/ 0x38 GPIOA INTCLEAR Interrupt clear register 0x0400 GPIOA LB_MASKED Lower byte masked access register 0x07FC reset value 0x0800 GPIOA UB_MASKED Upper byte maked access register 0x0BFC reset value 242 / 512 W7500 Datasheet Version1.0.0...
Page 243: Gpiob Registers(Address Base: 0X4300_0000)
DAO14 DAO13 DAO12 DAO11 DAO10 [15:0] DAOy(y = 0..15) READ as : Port out data bit WRITE as : WRITE to GPIOB_DATAOUT register 15.6.3 GPIOB Enable Set Register(GPIOB_OUTENSET) Address offset: 0x0010 Reset value: 0x0000 243 / 512 W7500 Datasheet Version1.0.0...
Page 244: Gpiob Enable Clear Register(Gpiob_Outenclr)
„1‟ is clears the output enable bit READ as : „0‟ is indicates the signal direction as input „1‟ is indicates the signal direction as output 15.6.5 GPIOB Interrupt Enable Set Register(GPIOB_ INTENSET) Address offset: 0x0020 Reset value: 0x0000 244 / 512 W7500 Datasheet Version1.0.0...
Page 245: Gpiob Interrupt Enable Clear Register(Gpiob_ Intenclr)
„1‟ is clears the interrupt enable bit READ as : „0‟ is indicates the interrupt disable „1‟ is indicates the interrupt enable 15.6.7 GPIOB Interrupt Type Set Register(GPIOB_ INTTYPESET) Address offset: 0x0028 Reset value: 0x---- 245 / 512 W7500 Datasheet Version1.0.0...
Page 246: Gpiob Interrupt Type Clear Register(Gpiob_ Inttypeclr)
„1‟ is clears the interrupt type bit READ as : „0‟ is indicates for LOW or HIGH level „1‟ is indicates for falling edge or rising edge 15.6.9 GPIOB Interrupt Polarity Set Register(GPIOB_ INTPOLSET) Address offset: 0x0030 Reset value: 0x---- 246 / 512 W7500 Datasheet Version1.0.0...
Page 247: Gpiob Interrupt Polarity Clear Register(Gpiob_ Intpolclr)
WRITE as : „0‟ is no effect „1‟ is clears the interrupt polarity bit READ as : „0‟ is indicates for LOW level or falling edge „1‟ is indicates for HIGH level or rising edge 247 / 512 W7500 Datasheet Version1.0.0...
Page 248: Gpiob Interrupt Status/Interrupt Clear Register
Lower eight bits masked access [15:8] Not used [7:0] Data for lower byte access, with bits[9:2] of address value used as enable bit mask for each bit 15.6.13 GPIOB Upper Byte Masked Access Register(GPIOB_ UB_MASKED) Address offset: 0x0800-0x0FC 248 / 512 W7500 Datasheet Version1.0.0...
Page 249 Reset value: 0x---- Higher eight bits masked access [15:8] Data for higher byte access, with bits[9:2] of address value used as enable bit mask for each bit [7:0] Not used 249 / 512 W7500 Datasheet Version1.0.0...
Page 250: Register Map
0x34 GPIOB INTSTATUS/ Interrupt status register/ 0x38 GPIOB INTCLEAR Interrupt clear register 0x0400 GPIOB LB_MASKED Lower byte masked access register 0x07FC reset value 0x0800 GPIOB UB_MASKED Upper byte maked access register 0x0BFC reset value 250 / 512 W7500 Datasheet Version1.0.0...
Page 251: Gpioc Registers(Address Base: 0X4400_0000)
DAO14 DAO13 DAO12 DAO11 DAO10 [15:0] DAOy(y = 0..15) READ as : Port out data bit WRITE as : WRITE to GPIOC_DATAOUT register 15.8.3 GPIOC Enable Set Register(GPIOC_OUTENSET) Address offset: 0x0010 Reset value: 0x0000 251 / 512 W7500 Datasheet Version1.0.0...
Page 252: Gpioc Enable Clear Register(Gpioc_Outenclr)
„1‟ is clears the output enable bit READ as : „0‟ is indicates the signal direction as input „1‟ is indicates the signal direction as output 15.8.5 GPIOC Interrupt Enable Set Register(GPIOC_ INTENSET) Address offset: 0x0020 Reset value: 0x0000 252 / 512 W7500 Datasheet Version1.0.0...
Page 253: Gpioc Interrupt Enable Clear Register(Gpioc_ Intenclr)
„1‟ is clears the interrupt enable bit READ as : „0‟ is indicates the interrupt disable „1‟ is indicates the interrupt enable 15.8.7 GPIOC Interrupt Type Set Register(GPIOC_ INTTYPESET) Address offset: 0x0028 Reset value: 0x---- 253 / 512 W7500 Datasheet Version1.0.0...
Page 254: Gpioc Interrupt Type Clear Register(Gpioc_ Inttypeclr)
„1‟ is clears the interrupt type bit READ as : „0‟ is indicates for LOW or HIGH level „1‟ is indicates for falling edge or rising edge 15.8.9 GPIOC Interrupt Polarity Set Register(GPIOC_ INTPOLSET) Address offset: 0x0030 Reset value: 0x---- 254 / 512 W7500 Datasheet Version1.0.0...
Page 255: Gpioc Interrupt Polarity Clear Register(Gpioc_ Intpolclr)
WRITE as : „0‟ is no effect „1‟ is clears the interrupt polarity bit READ as : „0‟ is indicates for LOW level or falling edge „1‟ is indicates for HIGH level or rising edge 255 / 512 W7500 Datasheet Version1.0.0...
Page 256: Gpioc Interrupt Status/Interrupt Clear Register
Address offset: 0x0400 – 0x07FC Reset value: 0x---- Lower eight bits masked access [15:8] Not used [7:0] Data for lower byte access, with bits[9:2] of address value used as enable bit mask for each bit 256 / 512 W7500 Datasheet Version1.0.0...
Page 257: Gpioc Upper Byte Masked Access Register(Gpioc_ Ub_Masked)
UB_MASKED) Address offset: 0x0800-0x0FC Reset value: 0x---- Higher eight bits masked access [15:8] Data for higher byte access, with bits[9:2] of address value used as enable bit mask for each bit [7:0] Not used 257 / 512 W7500 Datasheet Version1.0.0...
Page 258: Register Map
0x34 GPIOC INTSTATUS/ Interrupt status register/ 0x38 GPIOC INTCLEAR Interrupt clear register 0x0400 GPIOC LB_MASKED Lower byte masked access register 0x07FC reset value 0x0800 GPIOC UB_MASKED Upper byte maked access register 0x0BFC reset value 258 / 512 W7500 Datasheet Version1.0.0...
Page 259: Gpiod Registers(Address Base: 0X4500_0000)
DAO4 DAO3 DAO2 DAO1 DAO0 [15:0] DAOy(y = 0..15) READ as : Port out data bit WRITE as : WRITE to GPIOD_DATAOUT register 15.10.3 GPIOD Enable Set Register(GPIOD_OUTENSET) Address offset: 0x0010 Reset value: 0x0000 259 / 512 W7500 Datasheet Version1.0.0...
Page 260: Gpiod Enable Clear Register(Gpiod_Outenclr)
„1‟ is clears the output enable bit READ as : „0‟ is indicates the signal direction as input „1‟ is indicates the signal direction as output 15.10.5 GPIOD Interrupt Enable Set Register(GPIOD_ INTENSET) Address offset: 0x0020 Reset value: 0x0000 260 / 512 W7500 Datasheet Version1.0.0...
Page 261: Gpiod Interrupt Enable Clear Register(Gpiod_ Intenclr)
„1‟ is clears the interrupt enable bit READ as : „0‟ is indicates the interrupt disable „1‟ is indicates the interrupt enable 15.10.7 GPIOD Interrupt Type Set Register(GPIOD_ INTTYPESET) Address offset: 0x0028 Reset value: 0x---- 261 / 512 W7500 Datasheet Version1.0.0...
Page 262: Gpiod Interrupt Type Clear Register(Gpiod_ Inttypeclr)
„1‟ is clears the interrupt type bit READ as : „0‟ is indicates for LOW or HIGH level „1‟ is indicates for falling edge or rising edge 15.10.9 GPIOD Interrupt Polarity Set Register(GPIOD_ INTPOLSET) Address offset: 0x0030 Reset value: 0x---- 262 / 512 W7500 Datasheet Version1.0.0...
Page 263: Gpiod Interrupt Polarity Clear Register(Gpiod_ Intpolclr)
WRITE as : „0‟ is no effect „1‟ is clears the interrupt polarity bit READ as : „0‟ is indicates for LOW level or falling edge „1‟ is indicates for HIGH level or rising edge 263 / 512 W7500 Datasheet Version1.0.0...
Page 264: Gpiod Interrupt Status/Interrupt Clear Register
Address offset: 0x0400 – 0x07FC Reset value: 0x---- Lower eight bits masked access [15:8] Not used [7:0] Data for lower byte access, with bits[9:2] of address value used as enable bit mask for each bit 264 / 512 W7500 Datasheet Version1.0.0...
Page 265: Gpiod Upper Byte Masked Access Register(Gpiod_ Ub_Masked)
UB_MASKED) Address offset: 0x0800-0x0FC Reset value: 0x---- Higher eight bits masked access [15:8] Data for higher byte access, with bits[9:2] of address value used as enable bit mask for each bit [7:0] Not used 265 / 512 W7500 Datasheet Version1.0.0...
Page 266: Register Map
0x34 GPIOD INTSTATUS/ Interrupt status register/ 0x38 GPIOD INTCLEAR Interrupt clear register 0x0400 GPIOD LB_MASKED Lower byte masked access register 0x07FC reset value 0x0800 GPIOD UB_MASKED Upper byte maked access register 0x0BFC reset value 266 / 512 W7500 Datasheet Version1.0.0...
Page 267: Direct Memory Access Controller (Dma)
Figure 20 shows the DMA block diagram. TCP/IP GPIOA/GPIOB SRAM GPIO x 16 Other GPIOC/GPIOD Peripherals AHB-Lite BUS Bridge SPI0 Flash SRAM SPI1 Interface Controller uDMA UART0 (PL230) Flash SRAM DMA request UART1 Figure 20. DMA Block diagram 267 / 512 W7500 Datasheet Version1.0.0...
Page 268: Dma Request Mapping
DMA cycle types The cycle_ctrl bits in the channel control data structure controls how the DMA controller performs a cycle. The controller uses four cycle types described in this manual:  Invalid Basic  268 / 512 W7500 Datasheet Version1.0.0...
Page 269 The auto-request cycle is typically used for memory-to-memory requests. In this case, software generates the starting request for the transfers after setting up the DMA control data structure. 269 / 512 W7500 Datasheet Version1.0.0...
Page 270 (which is the value at the end of the last transfer using that structure), and the ping-pong cycle completes. The ping-pong cycle can be used for transfers to or from peripherals or for memory- to- memory transfers. 270 / 512 W7500 Datasheet Version1.0.0...
Page 271: Figure 21. Dma Ping Pong Cycle
Figure 21. DMA ping pong cycle 271 / 512 W7500 Datasheet Version1.0.0...
Page 272: Registers (Base Address : 0X4100_4000)
0110 : waiting channel controller data 1000 : stalled 1001 : done 1010 : peripheral scatter-gather transition 1011 – 1111 : undefined. 16.4.2 DMA configuration register (DMA_CFG) Address offset : 0x004 Reset value : - 272 / 512 W7500 Datasheet Version1.0.0...
Page 273: Dma Control Data Base Pointer Register (Dma_Ctrl_Base_Ptr)
These bits are read/write register. User must configure this register so that the base pointer points to a location in system memory. 16.4.4 DMA channel alternate control data base pointer register (DMA_ALT_CTRL_BASE_PTR) Address offset : 0x00c Reset value : 0x0000_0000 273 / 512 W7500 Datasheet Version1.0.0...
Page 274: Dma Channel Wait On Request Status Register (Dma_Waitonreq_Status)
[Channel-1] DMA_WAITONREQ – Channel wait on request status This read-only register returns the status of dma_waitonreq[Channel-1]. 0 : dma_waitonreq is low 1 : dma_waitonreq is high 16.4.6 DMA channel software request register (DMA_CHNL_SW_REQUEST) Address offset : 0x014 Reset value : - 274 / 512 W7500 Datasheet Version1.0.0...
Page 275: Dma Channel Useburst Set Register (Dma_Chnl_Useburst_Set)
1 : DMA [Channel-1] does not responds to requests that it receives on dma_sreq[Channel-1]. The controller only responds to dma_req[Channel-1] requests Write as : 0 : No effect. Use the CHNL_USEBURST_CLR register to set bit [Channel-1] to 0 275 / 512 W7500 Datasheet Version1.0.0...
Page 276: Dma Channel Useburst Clear Register (Dma_Chnl_Useburst_Clr)
DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) Address offset : 0x020 Reset value : 0x0000_0000 CHNL_REQ_MASK_SET[5:0] [Channel-1] CHNL_REQ_MASK_SET Returns request mask status dma_req[Channel-1] and dma_sreq[Channel-1], or disables the corresponding channel from generating DMA requests. 276 / 512 W7500 Datasheet Version1.0.0...
Page 277: Dma Channel Request Mask Clear Register (Dma_Chnl_Req_Mask_Clr)
0 : No effect. Use the CHNL_REQ_MASK_SET register to disable dma_req[Channel-1] and dma_sreq[Channel-1] from generating requests. 1 : Enables dma_req[Channel-1] or dma_sreq[Channel] to generate DMA requests. 16.4.11 DMA channel enable set register (DMA_CHNL_ENABLE_SET) Address offset : 0x028 Reset value : 0x0000_0000 277 / 512 W7500 Datasheet Version1.0.0...
Page 278: Dma Channel Enable Clear Register (Dma_Chnl_Enable_Clr)
This write only register disable a DMA channel. 0 : No effect. Use the CHNL_ENABLE_SET register to enable DMA channel. 1 : Disable channel [Channel-1] 16.4.13 DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) Address offset : 0x030 Reset value : 0x0000_0000 278 / 512 W7500 Datasheet Version1.0.0...
Page 279: Dma Channel Primary-Alternate Clear Register (Dma_Chnl_Pri_Alt
DMA channel. This write only register configures a DMA channels to use the primary data structure. 0 : No effect. Use the CHNL_PRI_ALT _SET register to select the alternate data structure. 279 / 512 W7500 Datasheet Version1.0.0...
Page 280: Dma Channel Priority Set Register (Dma_Chnl_Priority_Set)
0 – No effect. Use the CHNL_PRIORITY_CLR register to set bit [Channel-1] to default priority level 1 – Channel [Channel-1] uses the high priority level. 16.4.16 DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) Address offset : 0x03C Reset value : - CHNL_PRIORITY_CLR[5:0] 280 / 512 W7500 Datasheet Version1.0.0...
Page 281: Dma Bus Error Clear Register (Dma_Err_Clr)
This read/write register returns the status of DMA_ERR, and enables set DMA_ERR LOW. Read as : 0 : DMA_ERR is LOW 1 : DMA_ERR is HIGH Write as : 0 : No effect, status of DMA_ERR is unchanged. 1 : Sets DMA_ERR LOW. 281 / 512 W7500 Datasheet Version1.0.0...
Page 282: Register Map
CHNL_ENABLE_SET DMA_CHNL_ENABLE_SET 0x028 reset value CHNL_ENABLE_CLR DMA_CHNL_ENABLE_CLR 0x02C reset value CHNL_PRI_ALT_SET DMA_CHNL_PRI_ALT_SET 0x030 reset value CHNL_PRI_ALT_CLR DMA_CHNL_PRI_ALT_CLR 0x034 reset value CHNL_PRIORITY_SET DMA_CHNL_PRIORITY_SET 0x038 reset value DMA_CHNL_PRIORITY_CLR CHNL_PRIORITY_CLR 0x03C reset value DMA_ERR_CLR 0x04C reset value 282 / 512 W7500 Datasheet Version1.0.0...
Page 283: Analog-To-Digital Converter (Adc)
1 channel for internal LDO(1.5v) voltage. CH15 : Internal voltage  • Start of conversion can be initiated by software. • Convert selected inputs once per trigger. • Interrupt generation at the end of conversion. 283 / 512 W7500 Datasheet Version1.0.0...
Page 284: Functional Description
3. Run start ADC conversion by set ADC_SRT bit. 4. Check INT bit to know finish of conversion. 5. If INT bit is high (1), read ADC conversion data. 6. Finally, ADC operation is finished by setting the PWD bit. 284 / 512 W7500 Datasheet Version1.0.0...
Page 285: Figure 23. The Adc Operation Flowchart With Non-Interrupt
Select Channel (ADC_CHSEL) ADC Start (ADC_SRT) CHECK INT bit (INT == 1 ??) Read ADC conversion data (ADC_DATA) ADC again? ADC Power off (PWD = 1) Figure 23. The ADC operation flowchart with non-interrupt 285 / 512 W7500 Datasheet Version1.0.0...
Page 286: Operation Adc With Interrupt
ADC again? ADC Power off (PWD = 1) Figure 24. The ADC operation flowchart with interrupt 17.4 Registers (Base address : 0x4100_0000) 17.4.1 ADC control register (ADC_CTR) Address offset : 0x000 Reset value : 0x0000_0003 286 / 512 W7500 Datasheet Version1.0.0...
Page 287: Adc Channel Select Register (Adc_Chsel)
0001 : Channel 1 select 0010 : Channel 2 select 0011 : Channel 3 select 0100 : Channel 4 select 0101 : Channel 5 select 0110 : Channel 6 select 0111 : Channel 7 select 287 / 512 W7500 Datasheet Version1.0.0...
Page 288: Adc Start Register (Adc_Start)
Reset value : 0x0000_0000 ADC_DATA [11:0] ADC_DATA – ADC conversion result data It contains ADC conversion result data of last converted channel. These bits are read- only. 17.4.5 ADC Interrupt register (ADC_INT) Address offset : 0x010 288 / 512 W7500 Datasheet Version1.0.0...
Page 289: Adc Interrupt Clear Register (Adc_Intclr)
[0] INTCLR – Interrupt Clear bit. This bit set by S/W to clear interrupt signal to CM0. This bit is write-only. 0 – nothing 1 – Clear interrupt signal (This bit clear automatically after clear interrupt) 289 / 512 W7500 Datasheet Version1.0.0...
Page 290: Register Map
Table 20 ADC register map and reset values Offset Register ADC_CTR 0x000 reset value ADC_CHSEL CHSEL 0x004 reset value ADC_START 0x008 reset value DATA ADC_DATA 0x00C reset value ADC_INT 0x010 reset value ADC_INTCLR 0x01C reset value 290 / 512 W7500 Datasheet Version1.0.0...
Page 291: Pulse-Width Modulation (Pwm)
Channel 6 PWM output PWM 6 Prescale Channel 6 Register 0 ~ 7 Dead Zone generator Channel 7 Dead Zone generator PWM 7 Interrupt Register Channel 7 PWM output External input Figure 25 PWM block diagram 291 / 512 W7500 Datasheet Version1.0.0...
Page 292: Functional Description
The Timer/Counter has two repetition mode: periodic and one-shot mode. In periodic mode, the Timer/Counter recycles and then restarts when the Timer/Counter reaches the value of limit register. Figure 26 shows periodic mode timing diagram. PWMCLK Prescale Counter Timer/Counter Overflow Interrupt 292 / 512 W7500 Datasheet Version1.0.0...
Page 293: Figure 26 Periodic Mode
Timer/Counter restarts, if repetition mode is one-shot mode, the Timer/Counter stops. Figure 29 shows down-count mode timing diagram. PWMCLK Prescale Counter Timer/Counter Figure 29 Down-count mode Timer and Counter mode 293 / 512 W7500 Datasheet Version1.0.0...
Page 294: Figure 30 Counter Mode With Rising Edge
Figure 32 is with both rising and falling edge mode. External Input Start/Stop Register Rising edge detect Timer/Counter Figure 30 Counter mode with rising edge External Input Start/Stop Register Falling edge detect Timer/Counter Figure 31 Counter mode with falling edge 294 / 512 W7500 Datasheet Version1.0.0...
Page 295: Figure 32 Counter Mode With Rising And Falling Edge
2, match register is 2, limit register is 12, timer mode, periodic mode, up-count mode, and no interrupt clear. PWMCLK Start/Stop Register Prescale Counter Timer/Counter Prescale Counter Overflow Match Interrupt Interrupt Register[2:0] Figure 33 Timer/Counter timing diagram with match interrupt 295 / 512 W7500 Datasheet Version1.0.0...
Page 296: Pwm Mode
Figure 35 is an example of the PWM output waveform when the Timer/Counter is reached to the value of match register. Figure 36 is example of the PWM output waveform when to the Timer/Counter is reached to the value of limit register. 296 / 512 W7500 Datasheet Version1.0.0...
Page 297: Interrupt
Timer/Counter is reached to value of match register. The overflow interrupt occurs when the Timer/Counter is reached to value of limit register. The capture interrupt occurs when external input is entered for capture. 297 / 512 W7500 Datasheet Version1.0.0...
Page 298: Dead Zone Generation
Inverted PWM output Dead zone Dead zone Dead zone Dead zone Dead zone time time time time time Figure 37 PWM waveform with dead zone time 298 / 512 W7500 Datasheet Version1.0.0...
Page 299: Capture Event
There is no interrupt clear, so second capture does not save during second rising edge detection. External Input Rising edge detect Timer/Counter Capture Interrupt Capture register Capture Interrupt clear Interrupt Register[2:0] Figure 39 Capture event with no interrupt clear 299 / 512 W7500 Datasheet Version1.0.0...
Page 300: Figure 40 Capture Event With Interrupt Clear
Figure 40 shows, also, capture event timing diagram with interrupt clear. The second capture is saved at the second rising edge detection because there is interrupt clear. External Input Rising edge detect Timer/Counter Capture Interrupt Capture Interrupt clear Figure 40 Capture event with interrupt clear 300 / 512 W7500 Datasheet Version1.0.0...
Page 301: How To Set The Pwm
1 / Dead zone enable 0 / Dead zone disable CHn_CMR = CHn_CMR = 0 / rising edge capture 1 / falling edge capture Set the register: CHn_DZER Figure 41 The PWM setting flow 301 / 512 W7500 Datasheet Version1.0.0...
Page 302: Pwm Channel-0 Registers (Base Address : 0X4000_5000)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.4.2 Channel-0 interrupt enable register(PWMCH0IER) Base address : 0x4000_5000 Address offset : 0x04 Reset value : 0x0000_0000 302 / 512 W7500 Datasheet Version1.0.0...
Page 303: Channel-0 Interrupt Clear Register(Pwmch0Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.4.4 Channel-0 Timer/Counter Register (PWMCH0TCR) Base address : 0x4000_5000 Address offset : 0x0C Reset value : 0x0000_0000 303 / 512 W7500 Datasheet Version1.0.0...
Page 304: Channel-0 Prescale Counter Register (Pwmch0Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.4.6 Channel-0 Prescale Register (PWMCH0PR) Base address : 0x4000_5000 Address offset : 0x14 Reset value : 0x0000_0000 304 / 512 W7500 Datasheet Version1.0.0...
Page 305: Channel-0 Match Register (Pwmch0Mr)
Limit Register. The LR can generate an overflow interrupt and PWM output waveform becomes 1 when the TC is reached to the LR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1. 305 / 512 W7500 Datasheet Version1.0.0...
Page 306: Channel-0 Up-Down Mode Register (Pwmch0Udmr)
01 : Counter mode with counting driven by rising edge external input . 10 : Counter mode with counting driven by falling edge external input. 11 : Counter mode with counting driven by rising and falling edge external input. 306 / 512 W7500 Datasheet Version1.0.0...
Page 307: Channel-0 Pwm Output Enable And External Input Enable Register
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.4.13 Channel-0 Capture Register (PWMCH0CR) Base address : 0x4000_5000 Address offset : 0x30 307 / 512 W7500 Datasheet Version1.0.0...
Page 308: Channel-0 Periodic Mode Register (Pwmch0Pdmr)
1 : One-shot mode. When the TC is reached to the LR, the TC returns to 0 and then stops counting. 18.4.15 Channel-0 Dead Zone Enable Register (PWMCH0DZER) Base address : 0x4000_5000 Address offset : 0x38 Reset value : 0x0000_0000 308 / 512 W7500 Datasheet Version1.0.0...
Page 309: Channel-0 Dead Zone Counter Register (Pwmch0Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 309 / 512 W7500 Datasheet Version1.0.0...
Page 310: Register Map
PWMCH0CR Channel-0 Capture Register 0x30 reset value PWMCH0PDMR Channel-0 Periodic Mode Register 0x34 reset value Channel-0 Dead Zone Enable PWMCH0DZER 0x38 Register reset value Channel-0 Dead Zone Counter PWMCH0DZCR 0x3C Register reset value 310 / 512 W7500 Datasheet Version1.0.0...
Page 311: Pwm Channel-1 Registers (Base Address : 0X4000_5100)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.6.2 Channel-1 interrupt enable register(PWMCH1IER) Base address : 0x4000_5100 Address offset : 0x04 Reset value : 0x0000_0000 311 / 512 W7500 Datasheet Version1.0.0...
Page 312: Channel-1 Interrupt Clear Register(Pwmch1Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.6.4 Channel-1 Timer/Counter Register (PWMCH1TCR) Base address : 0x4000_5100 Address offset : 0x0C Reset value : 0x0000_0000 312 / 512 W7500 Datasheet Version1.0.0...
Page 313: Channel-1 Prescale Counter Register (Pwmch1Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.6.6 Channel-1 Prescale Register (PWMCH1PR) Base address : 0x4000_5100 Address offset : 0x14 Reset value : 0x0000_0000 313 / 512 W7500 Datasheet Version1.0.0...
Page 314: Channel-1 Match Register (Pwmch1Mr)
Limit Register. The LR can generate an overflow interrupt and PWM output waveform becomes 1 when the TC is reached to the LR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1. 314 / 512 W7500 Datasheet Version1.0.0...
Page 315: Channel-1 Up-Down Mode Register (Pwmch1Udmr)
01 : Counter mode with counting driven by rising edge external input . 10 : Counter mode with counting driven by falling edge external input. 11 : Counter mode with counting driven by rising and falling edge external input. 315 / 512 W7500 Datasheet Version1.0.0...
Page 316: Channel-1 Pwm Output Enable And External Input Enable Register
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.6.13 Channel-1 Capture Register (PWMCH1CR) Base address : 0x4000_5100 Address offset : 0x30 316 / 512 W7500 Datasheet Version1.0.0...
Page 317: Channel-1 Periodic Mode Register (Pwmch1Pdmr)
1 : One-shot mode. When the TC is reached to the LR, the TC returns to 0 and then stops counting. 18.6.15 Channel-1 Dead Zone Enable Register (PWMCH1DZER) Base address : 0x4000_5100 Address offset : 0x38 Reset value : 0x0000_0000 317 / 512 W7500 Datasheet Version1.0.0...
Page 318: Channel-1 Dead Zone Counter Register (Pwmch1Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 318 / 512 W7500 Datasheet Version1.0.0...
Page 319: Register Map
PWMCH1CR Channel-1 Capture Register 0x30 reset value PWMCH1PDMR Channel-1 Periodic Mode Register 0x34 reset value Channel-1 Dead Zone Enable PWMCH1DZER 0x38 Register reset value Channel-1 Dead Zone Counter PWMCH1DZCR 0x3C Register reset value 319 / 512 W7500 Datasheet Version1.0.0...
Page 320: Pwm Channel-2 Registers (Base Address : 0X4000_5200)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.8.2 Channel-2 interrupt enable register(PWMCH2IER) Base address : 0x4000_5200 Address offset : 0x04 Reset value : 0x0000_0000 320 / 512 W7500 Datasheet Version1.0.0...
Page 321: Channel-2 Interrupt Clear Register(Pwmch2Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.8.4 Channel-2 Timer/Counter Register (PWMCH2TCR) Base address : 0x4000_5200 Address offset : 0x0C Reset value : 0x0000_0000 321 / 512 W7500 Datasheet Version1.0.0...
Page 322: Channel-2 Prescale Counter Register (Pwmch2Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.8.6 Channel-2 Prescale Register (PWMCH2PR) Base address : 0x4000_5200 Address offset : 0x14 Reset value : 0x0000_0000 322 / 512 W7500 Datasheet Version1.0.0...
Page 323: Channel-2 Match Register (Pwmch2Mr)
1 when the TC is reached to the LR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1. 18.8.9 Channel-2 Up-Down Mode Register (PWMCH2UDMR) Base address : 0x4000_5200 323 / 512 W7500 Datasheet Version1.0.0...
Page 324: Channel-2 Timer/Counter Mode Register (Pwmch2Tcmr)
11 : Counter mode with counting driven by rising and falling edge external input. 18.8.11 Channel-2 PWM output Enable and External input Enable Register (PWMCH2PEEER) Base address : 0x4000_5200 Address offset : 0x28 Reset value : 0x0000_0000 324 / 512 W7500 Datasheet Version1.0.0...
Page 325: Channel-2 Capture Mode Register (Pwmch2Cmr)
1 : Timer/Counter is captured when external input signal is falling edge. 18.8.13 Channel-2 Capture Register (PWMCH2CR) Base address : 0x4000_5200 Address offset : 0x30 Reset value : 0x0000_0000 [31:0] CR – Capture Register 325 / 512 W7500 Datasheet Version1.0.0...
Page 326: Channel-2 Periodic Mode Register (Pwmch2Pdmr)
Channel-2 Dead Zone Enable Register (PWMCH2DZER) Base address : 0x4000_5200 Address offset : 0x38 Reset value : 0x0000_0000 [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. 326 / 512 W7500 Datasheet Version1.0.0...
Page 327: Channel-2 Dead Zone Counter Register (Pwmch2Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 327 / 512 W7500 Datasheet Version1.0.0...
Page 328: Register Map
PWMCH2CR Channel-2 Capture Register 0x30 reset value PWMCH2PDMR Channel-2 Periodic Mode Register 0x34 reset value Channel-2 Dead Zone Enable PWMCH2DZER 0x38 Register reset value Channel-2 Dead Zone Counter PWMCH2DZCR 0x3C Register reset value 328 / 512 W7500 Datasheet Version1.0.0...
Page 329: Pwm Channel-3 Registers (Base Address : 0X4000_5300)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.10.2 Channel-3 interrupt enable register(PWMCH3IER) Base address : 0x4000_5300 Address offset : 0x04 Reset value : 0x0000_0000 329 / 512 W7500 Datasheet Version1.0.0...
Page 330: Channel-3 Interrupt Clear Register(Pwmch3Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.10.4 Channel-3 Timer/Counter Register (PWMCH3TCR) Base address : 0x4000_5300 Address offset : 0x0C Reset value : 0x0000_0000 330 / 512 W7500 Datasheet Version1.0.0...
Page 331: Channel-3 Prescale Counter Register (Pwmch3Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.10.6 Channel-3 Prescale Register (PWMCH3PR) Base address : 0x4000_5300 Address offset : 0x14 Reset value : 0x0000_0000 331 / 512 W7500 Datasheet Version1.0.0...
Page 332: Channel-3 Match Register (Pwmch3Mr)
Limit Register. The LR can generate an overflow interrupt and PWM output waveform becomes 1 when the TC is reached to the LR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1. 332 / 512 W7500 Datasheet Version1.0.0...
Page 333: Channel-3 Up-Down Mode Register (Pwmch3Udmr)
01 : Counter mode with counting driven by rising edge external input . 10 : Counter mode with counting driven by falling edge external input. 11 : Counter mode with counting driven by rising and falling edge external input. 333 / 512 W7500 Datasheet Version1.0.0...
Page 334: Channel-3 Pwm Output Enable And External Input Enable Register
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.10.13 Channel-3 Capture Register (PWMCH3CR) Base address : 0x4000_5300 Address offset : 0x30 334 / 512 W7500 Datasheet Version1.0.0...
Page 335: Channel-3 Periodic Mode Register (Pwmch3Pdmr)
1 : One-shot mode. When the TC is reached to the LR, the TC returns to 0 and then stops counting. 18.10.15 Channel-3 Dead Zone Enable Register (PWMCH3DZER) Base address : 0x4000_5300 Address offset : 0x38 Reset value : 0x0000_0000 335 / 512 W7500 Datasheet Version1.0.0...
Page 336: Channel-3 Dead Zone Counter Register (Pwmch3Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 336 / 512 W7500 Datasheet Version1.0.0...
Page 337: Register Map
PWMCH3CR Channel-3 Capture Register 0x30 reset value PWMCH3PDMR Channel-3 Periodic Mode Register 0x34 reset value Channel-3 Dead Zone Enable PWMCH3DZER 0x38 Register reset value Channel-3 Dead Zone Counter PWMCH3DZCR 0x3C Register reset value 337 / 512 W7500 Datasheet Version1.0.0...
Page 338: Pwm Channel-4 Registers (Base Address : 0X4000_5400)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.12.2 Channel-4 interrupt enable register(PWMCH4IER) Base address : 0x4000_5400 Address offset : 0x04 Reset value : 0x0000_0000 338 / 512 W7500 Datasheet Version1.0.0...
Page 339: Channel-4 Interrupt Clear Register(Pwmch4Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.12.4 Channel-4 Timer/Counter Register (PWMCH4TCR) Base address : 0x4000_5400 Address offset : 0x0C Reset value : 0x0000_0000 339 / 512 W7500 Datasheet Version1.0.0...
Page 340: Channel-4 Prescale Counter Register (Pwmch4Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.12.6 Channel-4 Prescale Register (PWMCH4PR) Base address : 0x4000_5400 Address offset : 0x14 Reset value : 0x0000_0000 340 / 512 W7500 Datasheet Version1.0.0...
Page 341: Channel-4 Match Register (Pwmch4Mr)
If not, match interrupt is not occurred and PWM output waveform is always 1. 18.12.9 Channel-4 Up-Down Mode Register (PWMCH4UDMR) Base address : 0x4000_5400 Address offset : 0x20 Reset value : 0x0000_0000 341 / 512 W7500 Datasheet Version1.0.0...
Page 342: Channel-4 Timer/Counter Mode Register (Pwmch4Tcmr)
11 : Counter mode with counting driven by rising and falling edge external input. 18.12.11 Channel-4 PWM output Enable and External input Enable Register (PWMCH4PEEER) Base address : 0x4000_5400 Address offset : 0x28 Reset value : 0x0000_0000 342 / 512 W7500 Datasheet Version1.0.0...
Page 343: Channel-4 Capture Mode Register (Pwmch4Cmr)
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.12.13 Channel-4 Capture Register (PWMCH4CR) Base address : 0x4000_5400 Address offset : 0x30 Reset value : 0x0000_0000 343 / 512 W7500 Datasheet Version1.0.0...
Page 344: Channel-4 Periodic Mode Register (Pwmch4Pdmr)
Channel-4 Dead Zone Enable Register (PWMCH4DZER) Base address : 0x4000_5400 Address offset : 0x38 Reset value : 0x0000_0000 [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. 344 / 512 W7500 Datasheet Version1.0.0...
Page 345: Channel-4 Dead Zone Counter Register (Pwmch4Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 345 / 512 W7500 Datasheet Version1.0.0...
Page 346: Register Map
PWMCH4CR Channel-4 Capture Register 0x30 reset value PWMCH4PDMR Channel-4 Periodic Mode Register 0x34 reset value Channel-4 Dead Zone Enable PWMCH4DZER 0x38 Register reset value Channel-4 Dead Zone Counter PWMCH4DZCR 0x3C Register reset value 346 / 512 W7500 Datasheet Version1.0.0...
Page 347: Pwm Channel-5 Registers (Base Address : 0X4000_5500)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.14.2 Channel-5 interrupt enable register(PWMCH5IER) Base address : 0x4000_5500 Address offset : 0x04 Reset value : 0x0000_0000 347 / 512 W7500 Datasheet Version1.0.0...
Page 348: Channel-5 Interrupt Clear Register(Pwmch5Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.14.4 Channel-5 Timer/Counter Register (PWMCH5TCR) Base address : 0x4000_5500 Address offset : 0x0C Reset value : 0x0000_0000 348 / 512 W7500 Datasheet Version1.0.0...
Page 349: Channel-5 Prescale Counter Register (Pwmch5Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.14.6 Channel-5 Prescale Register (PWMCH5PR) Base address : 0x4000_5500 Address offset : 0x14 Reset value : 0x0000_0000 349 / 512 W7500 Datasheet Version1.0.0...
Page 350: Channel-5 Match Register (Pwmch5Mr)
1 when the TC is reached to the LR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1. 18.14.9 Channel-5 Up-Down Mode Register (PWMCH5UDMR) Base address : 0x4000_5500 350 / 512 W7500 Datasheet Version1.0.0...
Page 351: Channel-5 Timer/Counter Mode Register (Pwmch5Tcmr)
10 : Counter mode with counting driven by falling edge external input. 11 : Counter mode with counting driven by rising and falling edge external input. 18.14.11 Channel-5 PWM output Enable and External input Enable Register (PWMCH5PEEER) Base address : 0x4000_5500 Address offset : 0x28 351 / 512 W7500 Datasheet Version1.0.0...
Page 352: Channel-5 Capture Mode Register (Pwmch5Cmr)
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.14.13 Channel-5 Capture Register (PWMCH5CR) Base address : 0x4000_5500 Address offset : 0x30 Reset value : 0x0000_0000 352 / 512 W7500 Datasheet Version1.0.0...
Page 353: Channel-5 Periodic Mode Register (Pwmch5Pdmr)
Channel-5 Dead Zone Enable Register (PWMCH5DZER) Base address : 0x4000_5500 Address offset : 0x38 Reset value : 0x0000_0000 [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. 353 / 512 W7500 Datasheet Version1.0.0...
Page 354: Channel-5 Dead Zone Counter Register (Pwmch5Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 354 / 512 W7500 Datasheet Version1.0.0...
Page 355: Register Map
PWMCH5CR Channel-5 Capture Register 0x30 reset value PWMCH5PDMR Channel-5 Periodic Mode Register 0x34 reset value Channel-5 Dead Zone Enable PWMCH5DZER 0x38 Register reset value Channel-5 Dead Zone Counter PWMCH5DZCR 0x3C Register reset value 355 / 512 W7500 Datasheet Version1.0.0...
Page 356: Pwm Channel-6 Registers (Base Address : 0X4000_5600)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.16.2 Channel-6 interrupt enable register(PWMCH6IER) Base address : 0x4000_5600 Address offset : 0x04 Reset value : 0x0000_0000 356 / 512 W7500 Datasheet Version1.0.0...
Page 357: Channel-6 Interrupt Clear Register(Pwmch6Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.16.4 Channel-6 Timer/Counter Register (PWMCH6TCR) Base address : 0x4000_5600 Address offset : 0x0C Reset value : 0x0000_0000 357 / 512 W7500 Datasheet Version1.0.0...
Page 358: Channel-6 Prescale Counter Register (Pwmch6Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.16.6 Channel-6 Prescale Register (PWMCH6PR) Base address : 0x4000_5600 Address offset : 0x14 Reset value : 0x0000_0000 358 / 512 W7500 Datasheet Version1.0.0...
Page 359: Channel-6 Match Register (Pwmch6Mr)
1 when the TC is reached to the LR. Match register should be smaller than limit register(LR). If not, match interrupt is not occurred and PWM output waveform is always 1. 18.16.9 Channel-6 Up-Down Mode Register (PWMCH6UDMR) Base address : 0x4000_5600 359 / 512 W7500 Datasheet Version1.0.0...
Page 360: Channel-6 Timer/Counter Mode Register (Pwmch6Tcmr)
10 : Counter mode with counting driven by falling edge external input. 11 : Counter mode with counting driven by rising and falling edge external input. 18.16.11 Channel-6 PWM output Enable and External input Enable Register (PWMCH6PEEER) Base address : 0x4000_5600 Address offset : 0x28 360 / 512 W7500 Datasheet Version1.0.0...
Page 361: Channel-6 Capture Mode Register (Pwmch6Cmr)
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.16.13 Channel-6 Capture Register (PWMCH6CR) Base address : 0x4000_5600 Address offset : 0x30 Reset value : 0x0000_0000 361 / 512 W7500 Datasheet Version1.0.0...
Page 362: Channel-6 Periodic Mode Register (Pwmch6Pdmr)
Channel-6 Dead Zone Enable Register (PWMCH6DZER) Base address : 0x4000_5600 Address offset : 0x38 Reset value : 0x0000_0000 [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. 362 / 512 W7500 Datasheet Version1.0.0...
Page 363: Channel-6 Dead Zone Counter Register (Pwmch6Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 363 / 512 W7500 Datasheet Version1.0.0...
Page 364: Register Map
PWMCH6CR Channel-6 Capture Register 0x30 reset value PWMCH6PDMR Channel-6 Periodic Mode Register 0x34 reset value Channel-6 Dead Zone Enable PWMCH6DZER 0x38 Register reset value Channel-6 Dead Zone Counter PWMCH6DZCR 0x3C Register reset value 364 / 512 W7500 Datasheet Version1.0.0...
Page 365: Pwm Channel-7 Registers (Base Address : 0X4000_5700)
This bit is set by hardware and cleared by interrupt clear register. O : Capture interrupt does not occur. 1 : Capture interrupt occurs. 18.18.2 Channel-7 interrupt enable register(PWMCH7IER) Base address : 0x4000_5700 Address offset : 0x04 Reset value : 0x0000_0000 365 / 512 W7500 Datasheet Version1.0.0...
Page 366: Channel-7 Interrupt Clear Register(Pwmch7Icr)
1 : Overflow Interrupt is cleared. [2] CIC – Capture Interrupt Clear. O : No action. 1 : Capture Interrupt is cleared. 18.18.4 Channel-7 Timer/Counter Register (PWMCH7TCR) Base address : 0x4000_5700 Address offset : 0x0C Reset value : 0x0000_0000 366 / 512 W7500 Datasheet Version1.0.0...
Page 367: Channel-7 Prescale Counter Register (Pwmch7Pcr)
The PC is incremented to the value stored in PR. When the PC is reached to PR, the TC is incremented and the PC is reset as 0. 18.18.6 Channel-7 Prescale Register (PWMCH7PR) Base address : 0x4000_5700 Address offset : 0x14 Reset value : 0x0000_0000 367 / 512 W7500 Datasheet Version1.0.0...
Page 368: Channel-7 Match Register (Pwmch7Mr)
If not, match interrupt is not occurred and PWM output waveform is always 1. 18.18.9 Channel-7 Up-Down Mode Register (PWMCH7UDMR) Base address : 0x4000_5700 Address offset : 0x20 368 / 512 W7500 Datasheet Version1.0.0...
Page 369: Channel-7 Timer/Counter Mode Register (Pwmch7Tcmr)
10 : Counter mode with counting driven by falling edge external input. 11 : Counter mode with counting driven by rising and falling edge external input. 18.18.11 Channel-7 PWM output Enable and External input Enable Register (PWMCH7PEEER) Base address : 0x4000_5700 Address offset : 0x28 369 / 512 W7500 Datasheet Version1.0.0...
Page 370: Channel-7 Capture Mode Register (Pwmch7Cmr)
0 : Timer/Counter is captured when external input signal is rising edge. 1 : Timer/Counter is captured when external input signal is falling edge. 18.18.13 Channel-7 Capture Register (PWMCH7CR) Base address : 0x4000_5700 Address offset : 0x30 Reset value : 0x0000_0000 370 / 512 W7500 Datasheet Version1.0.0...
Page 371: Channel-7 Periodic Mode Register (Pwmch7Pdmr)
Channel-7 Dead Zone Enable Register (PWMCH7DZER) Base address : 0x4000_5700 Address offset : 0x38 Reset value : 0x0000_0000 [0] DZE – Dead Zone Enable 0 : Dead zone generation is disabled. 1 : Dead zone generation is enabled. 371 / 512 W7500 Datasheet Version1.0.0...
Page 372: Channel-7 Dead Zone Counter Register (Pwmch7Dzcr)
[9:0] DZC – Dead Zone Counter value Dead zone generation counter value register. If the DZE bit in DZER is 1, dead zone counter counts to this value and during this time, the two PWM output waveforms are all 0. 372 / 512 W7500 Datasheet Version1.0.0...
Page 373: Register Map
PWMCH7CR Channel-7 Capture Register 0x30 reset value PWMCH7PDMR Channel-7 Periodic Mode Register 0x34 reset value Channel-7 Dead Zone Enable PWMCH7DZER 0x38 Register reset value Channel-7 Dead Zone Counter PWMCH7DZCR 0x3C Register reset value 373 / 512 W7500 Datasheet Version1.0.0...
Page 374: Pwm Common Registers (Base Address : 0X4000_5800)
0 : Channel 6 interrupt is disabled. 1 : Channel 6 interrupt is enabled. [7] IE7 – Channel 7 Interrupt Enable 0 : Channel 7 interrupt is disabled. 1 : Channel 7 interrupt is enabled. 374 / 512 W7500 Datasheet Version1.0.0...
Page 375: Start/Stop Register (Ssr)
[6] SS6 – Channel 6 Timer/Counter Start or Stop. 0 : Timer/Counter stop. 1 : Timer/Counter start. [7] SS7 – Channel 7 Timer/Counter Start or Stop. 0 : Timer/Counter stop. 1 : Timer/Counter start. 375 / 512 W7500 Datasheet Version1.0.0...
Page 376: Pause Register (Psr)
[6] PS0 – Channel 6 Timer/Counter Pause. 0 : Timer/Counter is not paused. 1 : Timer/Counter is paused. [7] PS0 – Channel 7 Timer/Counter Pause. 0 : Timer/Counter is not paused. 1 : Timer/Counter is paused. 376 / 512 W7500 Datasheet Version1.0.0...
Page 377: Register Map
The following Table 29 summarizes the PWM Common registers. Table 29 PWM common register map and reset values Offset Register 비고 Interrupt enable register 0x00 reset value Start/Stop register 0x04 reset value Pause register 0x08 reset value 377 / 512 W7500 Datasheet Version1.0.0...
Page 378: Dual Timers
There is a prescaler that can divide down the clock rate by 1, 16, or 256.   Control Load Load BG Load BG Load Value Control IntClear Value 16-bit or 32-bit Counter Prescale counter 0x0000_0000 Clear Interrupt Interrupt Register Interrupt Figure 42 Block diagram of Dualtimer 378 / 512 W7500 Datasheet Version1.0.0...
Page 379: Functional Description
Write a new value to the Load Value register.  Wrapping mode Free-running mode The counter wraps after reaching its zero value, and continues to count down from the maximum value. This is the default mode. Periodic mode 379 / 512 W7500 Datasheet Version1.0.0...
Page 380: Interrupt
If users select periodic mode, the timer reloads the count value from the load register and continues to decrease. In this mode, the counter effectively generates a periodic interrupt. 380 / 512 W7500 Datasheet Version1.0.0...
Page 381: How To Set The Dual Timers
Wrapping or one-shot One-shot mode Wrapping mode TimerControl[0] =0 TimerControl[0] = 1 Wrapping mode : Free-running or Periodic mode Periodic mode Free-running mode TimerControl[0] =0 TimerControl[0] =1 Figure 43 The Dual timer setting flow 381 / 512 W7500 Datasheet Version1.0.0...
Page 382: Dual Timer0_0 Registers (Base Address : 0X4000_1000)
Reset value : 0xFFFF_FFFF [31:0] TVR – Timer Value Register This register provides the current value of the decrementing counter. 19.4.3 Timer0_0 Control Register(DUALTIMER0_0TimerControl) Base address : 0x4000_1000 Address offset : 0x08 Reset value : 0x0000_0020 382 / 512 W7500 Datasheet Version1.0.0...
Page 383: Timer0_0 Interrupt Clear Register (Dualtimer0_0Timerintclr)
1 : Timer enabled. 19.4.4 Timer0_0 Interrupt Clear Register (DUALTIMER0_0TimerIntClr) Base address : 0x4000_1000 Address offset : 0x0C [0] TIC – Interrupt Clear Set to this register clears the interrupt output from the counter. 383 / 512 W7500 Datasheet Version1.0.0...
Page 384: Timer0_0 Raw Interrupt Status Register (Dualtimer0_0Timerris)
AND of the raw interrupt status with the timer interrupt enable bit from the Timer Control Register, and is the same value that is passed to the interrupt output pin. 384 / 512 W7500 Datasheet Version1.0.0...
Page 385: Timer0_0 Background Load Register (Dualtimer0_0Timerbgload)
[31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. 385 / 512 W7500 Datasheet Version1.0.0...
Page 386: Register Map
DUALTIMER0_0TimerIntClr Register 0x0C reset value Write only register Timer0_0 Raw Interrupt Status DUALTIMER0_0TimerRIS Register 0x10 reset value Timer0_0 Masked Interrupt DUALTIMER0_0TimerMIS Status Register 0x14 reset value Timer0_0 Background Load DUALTIMER0_0TimerBGLoad Register 0x18 reset value 386 / 512 W7500 Datasheet Version1.0.0...
Page 387: Dual Timer0_1 Registers (Base Address : 0X4000_1020)
Reset value : 0xFFFF_FFFF [31:0] TVR – Timer Value Register This register provides the current value of the decrementing counter. 19.6.3 Timer0_1 Control Register(DUALTIMER0_1TimerControl) Base address : 0x4000_1020 Address offset : 0x08 Reset value : 0x0000_0020 387 / 512 W7500 Datasheet Version1.0.0...
Page 388: Timer0_1 Interrupt Clear Register (Dualtimer0_1Timerintclr)
Base address : 0x4000_1020 Address offset : 0x0C [0] IC – Interrupt Clear Set to the this register clears the interrupt output from the counter. 19.6.5 Timer0_1 Raw Interrupt Status Register (DUALTIMER0_1TimerRIS) Base address : 0x4000_1020 388 / 512 W7500 Datasheet Version1.0.0...
Page 389: Timer0_1 Masked Interrupt Status Register (Dualtimer0_1Timermis)
Timer Control Register, and is the same value that is passed to the interrupt output pin. 19.6.7 Timer0_1 Background Load Register (DUALTIMER0_1TimerBGLoad) Base address : 0x4000_1020 Address offset : 0x18 Reset value : 0x0000_0000 389 / 512 W7500 Datasheet Version1.0.0...
Page 390 [31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. 390 / 512 W7500 Datasheet Version1.0.0...
Page 391: Register Map
DUALTIMER0_1TimerIntClr Register 0x0C reset value Write only register Timer0_1 Raw Interrupt Status DUALTIMER0_1TimerRIS Register 0x10 reset value Timer0_1 Masked Interrupt DUALTIMER0_1TimerMIS Status Register 0x14 reset value Timer0_1 Background Load DUALTIMER0_1TimerBGLoad Register 0x18 reset value 391 / 512 W7500 Datasheet Version1.0.0...
Page 392: Dual Timer 0 Clock Enable Register (Base Address : 0X4000_1080)
1 : Clock enable 19.8.2 Timer0_1 Clock Enable Register (TIMCLKEN0_1) Base address : 0x4000_1080 Address offset : 0x20 Reset value : 0x0000_0000 [0] CE – Clock Enable Register 0 : Clock disable 1 : Clock enable 392 / 512 W7500 Datasheet Version1.0.0...
Page 393: Register Map
The following Table 32 summarizes the Dual timer 0 registers. Table 32 Dual timer 0 clock enable register map and reset values Offset Register 비고 Timer0_0 Clock Enable TIMCLKEN0_0 Register 0x00 reset value Timer0_1 Clock Enable TIMCLKEN0_1 Register 0x04 reset value 393 / 512 W7500 Datasheet Version1.0.0...
Page 394: Dual Timer1_0 Registers (Base Address : 0X4000_2000)
This register provides the current value of the decrementing counter. 19.10.3 Timer1_0 Control Register(DUALTIMER1_0TimerControl) Base address : 0x4000_2000 Address offset : 0x08 Reset value : 0x0000_0020 [0] OC – One-shot Count 0 : Wrapping mode, default. 394 / 512 W7500 Datasheet Version1.0.0...
Page 395: Timer1_0 Interrupt Clear Register (Dualtimer1_0Timerintclr)
[0] IC – Interrupt Clear Set to the this register clears the interrupt output from the counter. 19.10.5 Timer1_0 Raw Interrupt Status Register (DUALTIMER1_0TimerRIS) Base address : 0x4000_2000 Address offset : 0x10 Reset value : 0x0000_0000 395 / 512 W7500 Datasheet Version1.0.0...
Page 396: Timer1_0 Masked Interrupt Status Register (Dualtimer1_0Timermis)
Timer Control Register, and is the same value that is passed to the interrupt output pin. 19.10.7 Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad) Base address : 0x4000_2000 Address offset : 0x18 Reset value : 0x0000_0000 396 / 512 W7500 Datasheet Version1.0.0...
Page 397 [31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. 397 / 512 W7500 Datasheet Version1.0.0...
Page 398: Register Map
DUALTIMER1_0TimerIntClr Register 0x0C reset value Write only register Timer1_0 Raw Interrupt Status DUALTIMER1_0TimerRIS Register 0x10 reset value Timer1_0 Masked Interrupt DUALTIMER1_0TimerMIS Status Register 0x14 reset value Timer1_0 Background Load DUALTIMER1_0TimerBGLoad Register 0x18 reset value 398 / 512 W7500 Datasheet Version1.0.0...
Page 399: Dual Timer1_1 Registers (Base Address : 0X4000_2020)
This register provides the current value of the decrementing counter. 19.12.3 Timer1_1 Control Register(DUALTIMER1_1TimerControl) Base address : 0x4000_2020 Address offset : 0x08 Reset value : 0x0000_0020 [0] OC – One-shot Count 0 : Wrapping mode, default. 399 / 512 W7500 Datasheet Version1.0.0...
Page 400: Timer1_1 Interrupt Clear Register (Dualtimer1_1Timerintclr)
[0] IC – Interrupt Clear Set to the this register clears the interrupt output from the counter. 19.12.5 Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS) Base address : 0x4000_2020 Address offset : 0x10 Reset value : 0x0000_0000 400 / 512 W7500 Datasheet Version1.0.0...
Page 401: Timer1_1 Masked Interrupt Status Register (Dualtimer1_1Timermis)
Timer Control Register, and is the same value that is passed to the interrupt output pin. 19.12.7 Timer1_1 Background Load Register (DUALTIMER1_1TimerBGLoad) Base address : 0x4000_2020 Address offset : 0x18 Reset value : 0x0000_0000 401 / 512 W7500 Datasheet Version1.0.0...
Page 402 [31:0] BGL – Background Load Register This register contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches 0. 402 / 512 W7500 Datasheet Version1.0.0...
Page 403: Register Map
DUALTIMER1_1TimerIntClr Register 0x0C reset value Write only register Timer1_1 Raw Interrupt Status DUALTIMER1_1TimerRIS Register 0x10 reset value Timer1_1 Masked Interrupt DUALTIMER1_1TimerMIS Status Register 0x14 reset value Timer1_1 Background Load DUALTIMER1_1TimerBGLoad Register 0x18 reset value 403 / 512 W7500 Datasheet Version1.0.0...
Page 404: Dual Timer 1 Clock Enable Register (Base Address : 0X4000_2080)
1 : Clock enable 19.14.2 Timer1_1 Clock Enable Register (TIMCLKEN1_1) Base address : 0x4000_2080 Address offset : 0x20 Reset value : 0x0000_0000 [0] CE – Clock Enable Register 0 : Clock disable 1 : Clock enable 404 / 512 W7500 Datasheet Version1.0.0...
Page 405: Register Map
The following Table 35 summarizes the Dual timer 1 registers. Table 35 Dual timer 1 clock enable register map and reset values Offset Register 비고 Timer1_0 Clock Enable TIMCLKEN1_0 Register 0x00 reset value Timer1_1 Clock Enable TIMCLKEN1_1 Register 0x04 reset value 405 / 512 W7500 Datasheet Version1.0.0...
Page 406: Watchdog Timer
An interrupt is generated when the counter reaches 0 and is only cleared when the interrupt clear register is accessed. The register holds the value until the interrupt is cleared. Reset request is asserted when the counter reaches 0 repeatedly and is not reprogrammed. 406 / 512 W7500 Datasheet Version1.0.0...
Page 407: Watchdog Timer Registers (Base Address : 0X4000_0000)
The minimum valid value for WDTLoad is 1. 20.4.2 Watchdog timer Value Register(WDTValue) Address offset : 0x004 Reset value : 0xFFFF_FFFF [31:0] WVR – Watchdog timer Value Register. This register gives the current value of the decrementing counter. 407 / 512 W7500 Datasheet Version1.0.0...
Page 408: Watchdog Timer Control Register(Wdtcontrol)
A write of 1 to this register clears the watchdog interrupt, and reloads the counter from the value in WDTLoad. 20.4.5 Watchdog timer Raw Interrupt Status Register (WDTRIS) Address offset : 0x010 Reset value : 0x0000_0000 408 / 512 W7500 Datasheet Version1.0.0...
Page 409: Watchdog Timer Raw Interrupt Status Register (Wdtmis)
20.4.7 Watchdog timer Lock Register(WDTLock) Address offset : 0xC00 Reset value : 0x0000_0000 This register disables write accesses to all other registers. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 409 / 512 W7500 Datasheet Version1.0.0...
Page 410 0 : Indicates that write access is enabled, not locked. Default. 1 : Indicates that write access is disabled, locked. [31:1] ERW – Enable Register Writes Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value. 410 / 512 W7500 Datasheet Version1.0.0...
Page 411: Register Map
0x00C reset value Write only register Watchdog timer Raw Interrupt WDTRIS 0x010 Status Register reset value Watchdog timer Raw Interrupt WDTMIS Status Register 0x014 reset value WDTLock Watchdog timer Lock Register 0xC00 reset value 411 / 512 W7500 Datasheet Version1.0.0...
Page 412: Inter-Integrated Circuit Interface (I2C)
Figure 46 shows the I2C block diagram. In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupt is enabled or disabled by software. The 412 / 512 W7500 Datasheet Version1.0.0...
Page 413: Data Validity
SCL line is LOW (Figure 47). One clock pulse is generated for each data bit transferred. Data line Change of Stable data allowed Figure 47. Data Validity 413 / 512 W7500 Datasheet Version1.0.0...
Page 414: Acknowledge
A High to Low transition on the SDA line while SCL is High is one unique case and indicates a START condition. A Low to High transition on the SDA line while SCL is high defines a STOP condition. 414 / 512 W7500 Datasheet Version1.0.0...
Page 415: Slave Address
This address is seven bits followed by an eight bit which is a data direction bit(R/W) : „0‟ indicates a WRITE, „1‟ indicates a READ There are two methods of setting data direction bit by I2Cx_CTR. The 32-bits I2Cx_CTR is reconfigured with COREEN, INTEREN, MODE, ADDR10, CTRRWN, CTREN. 415 / 512 W7500 Datasheet Version1.0.0...
Page 416: Acknowledge(Ack) And Not Acknowledge(Nack)
By default, it operates in slave mode. The interface switches from slave to master when it generates the mode bit in the I2Cx_CTR. And COREEN bit in the I2Cx_CTR must be switched from 1 to 0. 416 / 512 W7500 Datasheet Version1.0.0...
Page 417: Interrupts
 Start conditions on bus detected Stop conditions on bus detected  Timeout error   Master transaction completed Slave transaction received  �� bus have separate interrupt signals. 417 / 512 W7500 Datasheet Version1.0.0...
Page 418: Master Mode
CTRW in I2Cx_CTR =0? CTR_WRITE CTR_READ depending on bit 0 of first byte MO DE in I2Cx_CTR =1 clear CORE_EN in I2Cx_CTR =1 Set I2Cx_PRE / I2Cx_TO Initia l E nd Figure 53. I2C initial setting 418 / 512 W7500 Datasheet Version1.0.0...
Page 419: Figure 54. Master Transmit With Addr10=0 In The I2Cx_Ctr
I2Cx_TR = {Slave Addr[7:1] ,READ or I2Cx_TR = Slave Addr[7:0] WRITE} STA/ACK in I2Cx_CMD = 1 ACK in I2Cx_SR ACK in I2Cx_SR Write I2Cx_TR ACK in I2Cx_SR ACK in I2Cx_SR Figure 54. Master TRANSMIT with ADDR10=0 in the I2Cx_CTR 419 / 512 W7500 Datasheet Version1.0.0...
Page 420: Figure 55. Master Transmit With Repeated Start
ACK in I2Cx_SR ACK in I2Cx_SR ACK in I2Cx_SR ACK in I2Cx_SR clear RESTA in I2Cx_CMD =1 Write I2Cx_TR BT in I2Cx_SR ACK in I2Cx_SR ACK in I2Cx_SR Figure 55. Master Transmit with Repeated START 420 / 512 W7500 Datasheet Version1.0.0...
Page 421: Slave Mode
Figure 56 shows the command sequences available for the �� slave. Slave initialization Set I2Cx_SADDR I2CxSADDR = Data? Send Ack I2CxSADDR[0] =1? Receive Data Transmit Data Receive Ack Send Ack STOE in I2Cx_ISR Figure 56. Slave Command Sequence 421 / 512 W7500 Datasheet Version1.0.0...
Page 422: I2C0 Registers(Base Address: 0X4000_8000)
The value should be greater than or equal to 4. �� Bit Freq(KHz) at �� (MHz) �� PRER 1000 2400 1500 1200 1000 [31:8] Reserved, must be kept at reset value The number of I2C, It means the 0,1 422 / 512 W7500 Datasheet Version1.0.0...
Page 423: I2C0 Control Register(I2C0_Ctr)
1: Master mode [6] INTEREN - Interrupt Enable 0: interrupt disable 1: interrupt enable [7] COREEN – Core Enable 0: core reset disable 1: core reset enable [31:8] Reserved, must be kept at reset value 423 / 512 W7500 Datasheet Version1.0.0...
Page 424: I2C0 Command Register(I2C0_Cmdr)
1: enable condition [7] STA – Start Condition (master mode) 0: disable Start condition 1: enable Start condition [31:8] Reserved, must be kept at reset value 21.4.4 I2C0 Status Register(I2C0_SR) Address offset: 0x0C Reset value: 0x0000_0000 424 / 512 W7500 Datasheet Version1.0.0...
Page 425 [9] TX – Transmit status This bit set by hardware when the data is transmitting and the data to be transmitted must be written in the I2C0_TXDR register. [31:10] Reserved, must be kept at reset value 425 / 512 W7500 Datasheet Version1.0.0...
Page 426: I2C0 Timeout Set Register(I2C0_Tsr)
[0] SADDR – Slave address bit 0 7-bit addressing mode(ADDR10=0) CTREN = 0 : It indicates a R/W bit CTREN = 1 : This bit are don‟t care [7:1] SADDR[7:1] – Slave address bit 7:1 7-bit addressing mode (ADDR10=0) 426 / 512 W7500 Datasheet Version1.0.0...
Page 427: I2C0 Transmit Register(I2C0_Txr)
[31:8] Reserved, must be kept at reset value 21.4.8 I2C0 Receive Register(I2C0_RXR) Address offset: 0x1C Reset value: 0x0000_0000 [7:0] RXD – 8-bit receive data Data byte received from the �� bus. [31:8] Reserved, must be kept at reset value 427 / 512 W7500 Datasheet Version1.0.0...
Page 428: I2C0 Interrupt Status Register(I2C0_Isr)
– or as a slave, provided that the peripheral has been addressed previously during this transfer. [31:5] Reserved, must be kept at reset value 21.4.10 I2C0 Interrupt Status Clear Register(I2C0_ISCR) Address offset: 0x24 Reset value: 0x0000_0000 428 / 512 W7500 Datasheet Version1.0.0...
Page 429: I2C0 Interrupt Status Mask Register(I2C0_Ismr)
Writing a 1 to this bit clears the TO bit in the I2C0_ISR register Writing 0 has no effect [3]STOEM – STOP detection flag clear (master mode) Writing a 1 to this bit clears the STOP bit in the I2C0_ISR register 429 / 512 W7500 Datasheet Version1.0.0...
Page 430 [4] STAEM – START detection flag clear (master mode) Writing a 1 to this bit clears the STA bit in the I2C0_ISR register Writing 0 has no effect [31:5] Reserved, must be kept at reset value 430 / 512 W7500 Datasheet Version1.0.0...
Page 431: Register Map
0x18 reset value Receive Data I2C0RXR Receive Register 0x1C reset value I2C0ISR Interrupt Status Register 0x20 reset value I2C0ISCR Interrupt Status Clear Register 0x24 reset value I2C0ISMR Interrupt Status Mask Register 0x28 reset value 431 / 512 W7500 Datasheet Version1.0.0...
Page 432: I2C1 Registers(Base Address : 0X4000_9000)
The value should be greater than or equal to 4. �� Bit Freq(KHz) at �� (MHz) �� PRER 1000 2400 1500 1200 1000 [31:8] Reserved, must be kept at reset value The number of I2C, It means the 0,1 432 / 512 W7500 Datasheet Version1.0.0...
Page 433: I2C1 Control Register(I2C1_Ctr)
1: Master mode [6] INTEREN - Interrupt Enable 0: interrupt disable 1: interrupt enable [7] COREEN – Core Enable 0: core reset disable 1: core reset enable [31:8] Reserved, must be kept at reset value 433 / 512 W7500 Datasheet Version1.0.0...
Page 434: I2C1 Command Register(I2C1_Cmdr)
1: enable condition [7] STA – Start Condition (master mode) 0: disable Start condition 1: enable Start condition [31:8] Reserved, must be kept at reset value 21.6.4 I2C1 Status Register(I2C1_SR) Address offset: 0x0C Reset value: 0x0000_0000 434 / 512 W7500 Datasheet Version1.0.0...
Page 435 [9] TX – Transmit status This bit set by hardware when the data is transmitting and the data to be transmitted must be written in the I2C1_TXDR register. [31:10] Reserved, must be kept at reset value 435 / 512 W7500 Datasheet Version1.0.0...
Page 436: I2C1 Timeout Set Register(I2C1_Tsr)
[0] SADDR – Slave address bit 0 7-bit addressing mode(ADDR10=0) CTREN = 0 : It indicates a R/W bit CTREN = 1 : This bit are don‟t care [7:1] SADDR[7:1] – Slave address bit 7:1 7-bit addressing mode (ADDR10=0) 436 / 512 W7500 Datasheet Version1.0.0...
Page 437: I2C1 Transmit Register(I2C1_Txr)
[31:8] Reserved, must be kept at reset value 21.6.8 I2C1 Receive Register(I2C1_RXR) Address offset: 0x1C Reset value: 0x0000_0000 [7:0] RXD – 8-bit receive data Data byte received from the �� bus. [31:8] Reserved, must be kept at reset value 437 / 512 W7500 Datasheet Version1.0.0...
Page 438: I2C1 Interrupt Status Register(I2C1_Isr)
– or as a slave, provided that the peripheral has been addressed previously during this transfer. [31:5] Reserved, must be kept at reset value 21.6.10 I2C1 Interrupt Status Clear Register(I2C1_ISCR) Address offset: 0x24 Reset value: 0x0000_0000 438 / 512 W7500 Datasheet Version1.0.0...
Page 439: I2C1 Interrupt Status Mask Register(I2C1_Ismr)
Writing a 1 to this bit clears the ACK_RECV bit in the I2C1_ISR register Writing 0 has no effect [2]TOEM - Timeout interrupt clear Writing a 1 to this bit clears the TO bit in the I2C1_ISR register 439 / 512 W7500 Datasheet Version1.0.0...
Page 440 [4] STAEM – START detection flag clear (master mode) Writing a 1 to this bit clears the STA bit in the I2C1_ISR register Writing 0 has no effect [31:5] Reserved, must be kept at reset value 440 / 512 W7500 Datasheet Version1.0.0...
Page 441: Register Map
0x18 reset value Receive Data I2C1RXR Receive Register 0x1C reset value I2C1ISR Interrupt Status Register 0x20 reset value I2C1ISCR Interrupt Status Clear Register 0x24 reset value I2C1ISMR Interrupt Status Mask Register 0x28 reset value 441 / 512 W7500 Datasheet Version1.0.0...
Page 442: Uart(Universal Asynchronous Receive Transmit)
1, 1.5, 2 Stop bits indicating that the frame is complete  The USART interface uses a baud rate generator  A status register (UART1_RISR)  data registers (UART1DR)  A baud rate register (UART1_IBRD,UART1_FBRD) 442 / 512 W7500 Datasheet Version1.0.0...
Page 443: Figure 57. Uart0,1 Block Diagram
Status nUARTDTR UARTEINTR nUARTRTS UARTINTR nUARTOut1 nUARTOut2 Figure 57. UART0,1 Block diagram Figure 58 shows the UART character frame Stop bits 5-8 data bits Start Parity bit, if enabled Figure 58. UART character frame 443 / 512 W7500 Datasheet Version1.0.0...
Page 444: Baud Rate Calculation
Figure 60 show how to set the UART Initial value. Initia l setting Start Setting UART baudra te Set UARTxLCR_H (Word length/Stop bit/Parity) Set UARTxCR (Mode/Hardwa reFlowControl) Figure 60. UART Initial setting flow chart 444 / 512 W7500 Datasheet Version1.0.0...
Page 445: Data Transmission
FIFO. Error bit is stored in bit[10:8] of UARTxCR and overrun is stored in bit[11] of UARTxCR. Initia l setting Set RTS/CTS of UARTxCR Set FEN of UARTxLCR_H Set RxSel/TxSel of UARTxIFLS Send Tx da ta receive Rx da ta Figure 61. Transmit and Receive data flow chart 445 / 512 W7500 Datasheet Version1.0.0...
Page 446: Hardware Flow Control
UARTx_TX bits0..7 stop start start bits0..7 stop start stop bit0..7 nUARTCTS Figure 63. CTS Functional Timing 446 / 512 W7500 Datasheet Version1.0.0...
Page 447: Figure 64. Algorithm For Setting Cts/Rts Flowchart
Set FEN of UARTxLCR_H Set RxSel/TxSel of UARTxIFLS CTS of UARTxFR =0? RXFE of UARTxFR =0? Send Tx da ta receive Rx da ta BUSY of UARTxFR =1? Figure 64. Algorithm for setting CTS/RTS flowchart 447 / 512 W7500 Datasheet Version1.0.0...
Page 448: Uart0 Registers(Base Address: 0X4000_C000)
UARTLCR_H [8] FE – Framing error 1: it indicates that the received [7:0] DATA – Receive (READ)/Transmit (WRITE) data 22.4.2 UART0RSR/ECR (UART0 Receive Status Register/Error Clear Register) Address offset: 0x004 Reset value: 0x0000_0000 448 / 512 W7500 Datasheet Version1.0.0...
Page 449: Uart0Fr (Uart0 Flag Register)
UART0FR (UART0 Flag Register) Address offset: 0x0018 Reset value: 0bx11000xxx TXFE RXFF TXFF RXFE BUSY [8] RI – Ring indicator This bit is the complement of the UART ring indicator, UART0RI. 1: When nUART0RI is LOW 449 / 512 W7500 Datasheet Version1.0.0...
Page 450: Uart0Ilpr (Uart0 Irda Low-Power Counter Register)
1: The bit is the complement of the UART clear to send 22.4.4 UART0ILPR (UART0 IrDA Low-Power Counter Register) Address offset: 0x0020 Reset value: 0x00 The UARTILPR Register is the IrDA low-power counter register 450 / 512 W7500 Datasheet Version1.0.0...
Page 451: Uart0Ibrd (Uart0 Integer Baud Rate Register)
These bits are cleared to 0 on reset 22.4.6 UART0FBRD (UART0 Fractional Baud Rate Register) Address offset: 0x0028 Reset value: 0x00 The UART0FBRD register is the fractional part of the baud rate divisor value. 451 / 512 W7500 Datasheet Version1.0.0...
Page 452: Uart0Lcr_H (Uart0 Line Control Register)
22.4.7 UART0LCR_H (UART0 Line Control Register) Address offset: 0x002C Reset value: 0x00 The UART0LCR_H register is the line control register. This register accesses bits 29 to 22 of the UART line control register, UART0LCR. 452 / 512 W7500 Datasheet Version1.0.0...
Page 453 [0] BRK – Send break 0: For normal use, the bit must be cleared to 0 1: The low-level is continually output on the UARTTXD output Parity bit(Transmitted or checked) Not transmitted or checked Even parity Odd parity 453 / 512 W7500 Datasheet Version1.0.0...
Page 454: Uart0Cr (Uart0 Control Register)
Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. 454 / 512 W7500 Datasheet Version1.0.0...
Page 455: Uart0Ifls (Uart0 Interrupt Fifo Level Select Register)
Reset value: 0x12 The UARTIFLS register is the interrupt FIFO level select register. RXIFLSEL TXIFLSEL [5:3] RXIFLSEL – Receive interrupt FIFO level select Reserved 7/8 full 3/4 full 1/2 full 1/4 full 1/8 full 455 / 512 W7500 Datasheet Version1.0.0...
Page 456: Uart0Imsc (Uart0 Interrupt Mask Set/Clear Register)
1: Enable UART0FEINTR [6] RTIM – Receive timeout interrupt mask 0: Disable UART0RTINTR 1: Enable UART0RTINTR [5] TXIM – Transmit interrupt mask 0: Disable UART0TXINTR 1: Enable UART0TXINTR [4] RXIM – Receive interrupt mask 456 / 512 W7500 Datasheet Version1.0.0...
Page 457: Uart0Ris (Uart0 Raw Interrupt Status Register)
It indicates state of the UART0FEINTR interrupt. [6] RTRIS – Receive timeout interrupt status It indicates state of the UART0RTINTR interrupt. [5] TXRIS – Transmit interrupt status It indicates state of the UART0TXINTR interrupt. 457 / 512 W7500 Datasheet Version1.0.0...
Page 458: Uart0Mis (Uart0 Masked Interrupt Status Register)
[5] TXMIS – Transmit masked interrupt status It indicates state of the UART0TXINTR interrupt. [4] RXMIS – Receive masked interrupt status It indicates state of the UART0RXINTR interrupt. [3] DSRMMIS – nUART0DSR modem masked interrupt status 458 / 512 W7500 Datasheet Version1.0.0...
Page 459: Uart0Icr (Uart0 Interrupt Clear Register)
Clear the UART0TXINTR interrupt. [4] RXIC – Receive interrupt clear Clear the UART0RXINTR interrupt. [3] DSRMIC – nUART0DSR modem interrupt clear Clear the UART0DSRINTR interrupt. [2] DCDMIC – nUART0DCD modem interrupt clear Clear the UART0DCDINTR interrupt. 459 / 512 W7500 Datasheet Version1.0.0...
Page 460 [1] CTSMIC – nUART0CTS modem interrupt clear Clear the UART0CTSINTR interrupt. [0] RIMIC – nUART0RI modem interrupt clear Clear the UART0RIINTR interrupt. 460 / 512 W7500 Datasheet Version1.0.0...
Page 461: Register Map
Interrupt FIFO Level Select Register reset value 0x038 UART0IMSC Interrupt Mask Set/Clear Register reset value 0x03C UART0RIS Raw Interrupt Status Register reset value 0x040 UART0MIS Masked Interrupt StatusRegister reset value 0x044 UART0ICR Interrupt Clear Register reset value 461 / 512 W7500 Datasheet Version1.0.0...
Page 462: Uart1 Registers(Base Address: 0X4000_D000)
1: it indicates that the received [7:0] DATA – Receive (READ)/Transmit (WRITE) data 22.6.2 UART1RSR/ECR (UART1 Receive Status Register/Error Clear Register) Address offset: 0x004 Reset value: 0x0000_0000 The UART1RSR/ECR is the receive status register/error clear register. 462 / 512 W7500 Datasheet Version1.0.0...
Page 463: Uart1Fr (Uart1 Flag Register)
Reset value: 0bx11000xxx TXFE RXFF TXFF RXFE BUSY [8] RI – Ring indicator This bit is the complement of the UART ring indicator, UART1RI. 1: When nUART1RI is LOW [7] TXFE – Transmit FIFO empty 463 / 512 W7500 Datasheet Version1.0.0...
Page 464: Uart1Ilpr (Uart1 Irda Low-Power Counter Register)
1: The bit is the complement of the UART clear to send 22.6.4 UART1ILPR (UART1 IrDA Low-Power Counter Register) Address offset: 0x0020 Reset value: 0x00 The UARTILPR Register is the IrDA low-power counter register 464 / 512 W7500 Datasheet Version1.0.0...
Page 465: Uart1Ibrd (Uart1 Integer Baud Rate Register)
These bits are cleared to 0 on reset 22.6.6 UART1FBRD (UART1 Fractional Baud Rate Register) Address offset: 0x0028 Reset value: 0x00 The UART1FBRD register is the fractional part of the baud rate divisor value. BAUD DIVFRAC 465 / 512 W7500 Datasheet Version1.0.0...
Page 466: Uart1Lcr_H (Uart1 Line Control Register)
22.6.7 UART1LCR_H (UART1 Line Control Register) Address offset: 0x002C Reset value: 0x00 The UART1LCR_H register is the line control register. This register accesses bits 29 to 22 of the UART line control register, UART1LCR. 466 / 512 W7500 Datasheet Version1.0.0...
Page 467 [0] BRK – Send break 0: For normal use, the bit must be cleared to 0 1: The low-level is continually output on the UARTTXD output Parity bit(Transmitted or checked) Not transmitted or checked Even parity Odd parity 467 / 512 W7500 Datasheet Version1.0.0...
Page 468: Uart1Cr (Uart1 Control Register)
Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. 468 / 512 W7500 Datasheet Version1.0.0...
Page 469: Uart1Ifls (Uart1 Interrupt Fifo Level Select Register)
Reset value: 0x12 The UARTIFLS register is the interrupt FIFO level select register. RXIFLSEL TXIFLSEL [5:3] RXIFLSEL – Receive interrupt FIFO level select Reserved 7/8 full 3/4 full 1/2 full 1/4 full 1/8 full 469 / 512 W7500 Datasheet Version1.0.0...
Page 470: Uart1Imsc (Uart1 Interrupt Mask Set/Clear Register)
1: Enable UART1FEINTR [6] RTIM – Receive timeout interrupt mask 0: Disable UART1RTINTR 1: Enable UART1RTINTR [5] TXIM – Transmit interrupt mask 0: Disable UART1TXINTR 1: Enable UART1TXINTR [4] RXIM – Receive interrupt mask 470 / 512 W7500 Datasheet Version1.0.0...
Page 471: Uart1Ris (Uart1 Raw Interrupt Status Register)
It indicates state of the UART1FEINTR interrupt. [6] RTRIS – Receive timeout interrupt status It indicates state of the UART1RTINTR interrupt. [5] TXRIS – Transmit interrupt status It indicates state of the UART1TXINTR interrupt. 471 / 512 W7500 Datasheet Version1.0.0...
Page 472: Uart1Mis (Uart1 Masked Interrupt Status Register)
It indicates state of the UART1TXINTR interrupt. [4] RXMIS – Receive masked interrupt status It indicates state of the UART1RXINTR interrupt. [3] DSRMMIS – nUART1DSR modem masked interrupt status It indicates state of the UART1DSRINTR interrupt. 472 / 512 W7500 Datasheet Version1.0.0...
Page 473: Uart1Icr (Uart1 Interrupt Clear Register)
Clear the UART1TXINTR interrupt. [4] RXIC – Receive interrupt clear Clear the UART1RXINTR interrupt. [3] DSRMIC – nUART1DSR modem interrupt clear Clear the UART1DSRINTR interrupt. [2] DCDMIC – nUART1DCD modem interrupt clear Clear the UART1DCDINTR interrupt. 473 / 512 W7500 Datasheet Version1.0.0...
Page 474 [1] CTSMIC – nUART1CTS modem interrupt clear Clear the UART1CTSINTR interrupt. [0] RIMIC – nUART1RI modem interrupt clear Clear the UART1RIINTR interrupt. 474 / 512 W7500 Datasheet Version1.0.0...
Page 475: Register Map
Interrupt FIFO Level Select Register reset value 0x038 UART1IMSC Interrupt Mask Set/Clear Register reset value 0x03C UART1RIS Raw Interrupt Status Register reset value 0x040 UART1MIS Masked Interrupt StatusRegister reset value 0x044 UART1ICR Interrupt Clear Register reset value 475 / 512 W7500 Datasheet Version1.0.0...
Page 476: Synchronous Serial Port (Ssp)
Programmable clock bit rate and prescaler. The input clock may be divided by a  factor of 2 to 254 in steps of two to provide the serial output clock Programmable clock phase and polarity.  476 / 512 W7500 Datasheet Version1.0.0...
Page 477: Functional Description
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and is transmitted to the attached slave or master through the SSPTXD pin. 477 / 512 W7500 Datasheet Version1.0.0...
Page 478: Receive Fifo
Receive – The DMA interface includes the following signals for receive: SSPRXDMASREQ Single-character DMA transfer request asserted by the SSP. This signal is  asserted when the receive FIFO contains at least one character. SSPRXDMABREQ 478 / 512 W7500 Datasheet Version1.0.0...
Page 479: Table 41 Dma Trigger Points For The Transmit And Receive Fifos
Table 41 shows the trigger points for DMABREQ of both the transmit and receive FIFOs. Table 41 DMA trigger points for the transmit and receive FIFOs. Burst length Watermark Transmit, number of empty locations Receive, number of filled locations 479 / 512 W7500 Datasheet Version1.0.0...
Page 480: Interface Reset
• Motorola SPI • Texas Instruments SSI • National Semiconductor. The bit rate, derived from the external SSPCLK, requires the programming of the clock prescale register SSPCPSR. 480 / 512 W7500 Datasheet Version1.0.0...
Page 481: Enable Primecell Ssp Operation
12 and the SCR[7:0] field in the SSPCR0 register can be programmed with a value of 0. Similarly, the ratio of SSPCLK maximum frequency to SSPCLKOUT minimum frequency is 254 x 256. 481 / 512 W7500 Datasheet Version1.0.0...
Page 482: Programming The Sspcr0 Control Register
To configure the PrimeCell SSP as a master, clear the SSPCR1 register master or slave selection bit, MS, to 0. This is the default value on reset. Setting the SSPCR1 register MS bit to 1 configures the PrimeCell SSP as a slave. When 482 / 512 W7500 Datasheet Version1.0.0...
Page 483: Frame Format
FIFO still contains data after a timeout period. For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame SSPFSSOUT pin is active-LOW and is asserted and pulled-down during the entire transmission of the frame. 483 / 512 W7500 Datasheet Version1.0.0...
Page 484: Texas Instruments Synchronous Serial Frame Format
SSPRXD pin by the off-chip serial slave device. Both the PrimeCell SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSPCLKOUT. The received data is transferred 484 / 512 W7500 Datasheet Version1.0.0...
Page 485: Motorola Spi Frame Format
When the SPH clock phase control bit is HIGH, data is captured on the second clock edge transition. Figure 69 and Figure 70 show single and continuous transmission signal sequences for Motorola SPI format with SPO=0, SPH=0. 485 / 512 W7500 Datasheet Version1.0.0...
Page 486: Figure 69 Motorola Spi Frame Format, Single Transfer, With Spo=0 And Sph=0
SSPFSSOUT master signal being driven LOW. This causes the slave data to be enabled onto the SSPRXD input line of the master. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad. 486 / 512 W7500 Datasheet Version1.0.0...
Page 487: Figure 71 Motorola Spi Frame Format, Single And Continuous Transfers, With Spo=0 And
Figure 71 Motorola SPI frame format, single and continuous transfers, with SPO=0 and SPH=1 In this configuration, during idle periods: • the SSPCLKOUT signal is forced LOW • The SSPFSSOUT signal is forced HIGH • the transmit data line SSPTXD is arbitrarily forced LOW 487 / 512 W7500 Datasheet Version1.0.0...
Page 488: Figure 72 Motorola Spi Frame Format, Single Transfer, With Spo=1 And Sph=0
Figure 72 Motorola SPI frame format, single transfer, with SPO=1 and SPH=0 Figure 73 shows a continuous transmission signal sequence for Motorola SPI format with SPO=1, SPH=0. In Figure 9, Q is an undefined signal. 488 / 512 W7500 Datasheet Version1.0.0...
Page 489: Figure 73. Motorola Spi Frame Format, Continuous Transfers, With Spo=1 And Sph=0
SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the 489 / 512 W7500 Datasheet Version1.0.0...
Page 490: Figure 74. Motorola Spi Frame Format, Single And Continuous Transfers, With Spo
After all bits have been transferred in the case of a single word transmission, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured. 490 / 512 W7500 Datasheet Version1.0.0...
Page 491: National Semiconductor Microwire Frame Format
• the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance. A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSPFSSOUT causes the value contained in the bottom entry of the transmit FIFO to be 491 / 512 W7500 Datasheet Version1.0.0...
Page 492: Figure 76. National Semiconductor Microwire Frame Format, Continuous Transfers
Figure 76 shows the National Semiconductor Microwire frame format when back-to-back frames are transmitted. SSPCLKOUT/ SSPCLKIN SSPFSSOUT/ SSPFSSIN SSPTXD 4 to 16 bits 8-bit control output data SSPRXD nSSPOE Figure 76. National Semiconductor Microwire frame format, continuous transfers 492 / 512 W7500 Datasheet Version1.0.0...
Page 493: Master And Slave Configurations
SPI MOSI line. In response, the slave drives its nSSPOE signal LOW. This enables its SSPTXD data onto the MISO line of the master. MOSI SSPRXD nSSPOE MISO SSPTXD SSPFSSIN SSPCLKIN SSPFSSOUT nSSPCTLOE SSPCLKOUT Figure 78. SPI master coupled to a PrimeCell SSP slave 493 / 512 W7500 Datasheet Version1.0.0...
Page 494: Ssp Flow Chart
(Slave Output Mode Setting Disable) Setting (choose Slave) DataSize Setting (choose 4~16bits) (Syncronous Serialport Enable) Setting (Syncronous Serialport Enable) Setting BaudRatePrescaler Setting (4~254) Figure 79. how to setting TI or Microwire mode flow chart 494 / 512 W7500 Datasheet Version1.0.0...
Page 495: Figure 80. How To Setting Spi Mode Flow Chart
Disable) Setting (Slave Output Mode Setting Disable) Setting (choose Slave) DataSize Setting (choose 4~16bits) (Syncronous Serialport Enable) Setting (Syncronous Serialport Enable) Setting BaudRatePrescaler Setting (4~254) Figure 80. how to setting SPI mode flow chart 495 / 512 W7500 Datasheet Version1.0.0...
Page 496: Ssp0 Registers (Base Address : 0X4000_A000)
The value SCR is used to generate the transmit and receive bit rate of the SSP. The bit rate is: fSSPCLK / (CPSDVR * (1 + SCR)) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. 496 / 512 W7500 Datasheet Version1.0.0...
Page 497: Ssp0 Control Register 1 (Ssp0Cr1)
0 : SSP0 can drive the SSPTXD output in slave mode. 1 : SSP0 must not drive the SSPTXD output in slave mode. 23.4.3 SSP0 Data register (SSP0DR) Address offset: 0x0008 Reset value: 0x0000_0000 497 / 512 W7500 Datasheet Version1.0.0...
Page 498: Ssp0 Status Register (Ssp0Sr)
1 : Receive FIFO is not empty. [3] RFF – Receive FIFO full, RO: 0 : Receive FIFO is not full. 1 : Receive FIFO is full. [4] BSY – SSP busy flag, RO: 0 : SSP is idle.No effect 498 / 512 W7500 Datasheet Version1.0.0...
Page 499: Ssp0 Clock Prescale Register (Ssp0Cpsr)
1 : Receive FIFO written to while full condition interrupt is not masked. [1] RTIM – Receive timeout interrupt mask: 0 : Receive FIFO not empty and no read prior to timeout period interrupt is masked. 499 / 512 W7500 Datasheet Version1.0.0...
Page 500: Ssp0 Raw Interrupt Status Register (Ssp0Ris)
[2] RXRIS – Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [3] TXRIS – Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt 23.4.8 SSP0 Masked interrupt status register, (SSP0MIS) Address offset: 0x001C Reset value: 0x0000_00000 500 / 512 W7500 Datasheet Version1.0.0...
Page 501: Ssp0 Interrupt Clear Register (Ssp0Icr)
SSP0 Interrupt clear register (SSP0ICR) Address offset: 0x0020 Reset value: 0x0000_00000 RTIC [0] RORICS – Clears the SSPRORINTR interrupt [1] RTIC – Clears the SSPRTINTR interrupt 23.4.10 SSP0 DMA control register, (SSP0DMACR) Address offset: 0x0024 Reset value: 0x0000_00000 501 / 512 W7500 Datasheet Version1.0.0...
Page 502 0 : DMA for the receive FIFO is disabled. 1 : DMA for the receive FIFO is enabled. [1] TXDMAE – Transmit DMA Enable: 0 : DMA for the transmit FIFO is disabled. 1 : DMA for the transmit FIFO is enabled. 502 / 512 W7500 Datasheet Version1.0.0...
Page 503: Register Map
Interrupt Mask set or clear register 0x14 reset value SSPRIS Raw interrupt status register 0x18 reset value SSPMIS Masked interrupt status register 0x1C reset value SSPICR Interrupt clear register 0x20 reset value SSPDMACR DMA control regsiter 0x24 reset value 503 / 512 W7500 Datasheet Version1.0.0...
Page 504: Ssp1 Registers (Base Address : 0X4000_B000)
The value SCR is used to generate the transmit and receive bit rate of the SSP. The bit rate is: fSSPCLK / (CPSDVR * (1 + SCR)) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. 504 / 512 W7500 Datasheet Version1.0.0...
Page 505: Ssp1 Control Register 1 (Ssp1Cr1)
To operate in such systems, the SOD bit can be set if the SSP1 slave is not supposed to drive the SSPTXD line: 0 : SSP1 can drive the SSPTXD output in slave mode. 1 : SSP1 must not drive the SSPTXD output in slave mode. 505 / 512 W7500 Datasheet Version1.0.0...
Page 506: Ssp1 Data Register (Ssp1Dr)
0 : Transmit FIFO is full. 1 : Transmit FIFO is not full. [2] RNE – Receive FIFO not empty, RO: 0 : Receive FIFO is empty. 1 : Receive FIFO is not empty. 506 / 512 W7500 Datasheet Version1.0.0...
Page 507: Ssp1 Clock Prescale Register (Ssp1Cpsr)
23.6.6 SSP1 Interrupt mask set or clear register (SSP1IMSC) Address offset: 0x0014 Reset value: 0x0000_00000 [0] RORIM – Receive overrun interrupt mask: 0 : Receive FIFO written to while full condition interrupt is masked. 507 / 512 W7500 Datasheet Version1.0.0...
Page 508: Ssp1 Raw Interrupt Status Register (Ssp1Ris)
[2] RXRIS – Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [3] TXRIS – Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt 23.6.8 SSP1 Masked interrupt status register, (SSP1MIS) Address offset: 0x001C Reset value: 0x0000_00000 508 / 512 W7500 Datasheet Version1.0.0...
Page 509: Ssp1 Interrupt Clear Register (Ssp1Icr)
SSP1 Interrupt clear register (SSP1ICR) Address offset: 0x0020 Reset value: 0x0000_00000 RTIC [0] RORICS – Clears the SSPRORINTR interrupt [1] RTIC – Clears the SSPRTINTR interrupt 23.6.10 SSP1 DMA control register, (SSP1DMACR) Address offset: 0x0024 Reset value: 0x0000_00000 509 / 512 W7500 Datasheet Version1.0.0...
Page 510 0 : DMA for the receive FIFO is disabled. 1 : DMA for the receive FIFO is enabled. [1] TXDMAE – Transmit DMA Enable: 0 : DMA for the transmit FIFO is disabled. 1 : DMA for the transmit FIFO is enabled. 510 / 512 W7500 Datasheet Version1.0.0...
Page 511: Register Map
Interrupt Mask set or clear register 0x14 reset value SSPRIS Raw interrupt status register 0x18 reset value SSPMIS Masked interrupt status register 0x1C reset value SSPICR Interrupt clear register 0x20 reset value SSPDMACR DMA control regsiter 0x24 reset value 511 / 512 W7500 Datasheet Version1.0.0...
Page 512: Document History Information
Document History Information Version Date Descriptions Ver. 1.0.0 01MAY2015 Initial Release Copyright Notice Copyright 2015 WIZnet Co., Ltd. All Rights Reserved. Technical Support: http://wizwiki.net/forum Sales & Distribution: sales@wiznet.co.kr For more information, visit our website at http://www.wiznet.co.kr 512 / 512 W7500 Datasheet Version1.0.0...

Wiznet W7500 Reference Manual

1 Documentation Conventions

2 System and Memory Overview

3 System Configuration Controller (SYSCFG)

4 Interrupt and Events

5 Power Supply

6 System Tick Timer

7 Tcpipcore Offload Engine (TOE)

8 Booting Sequence

9 Embedded Flash Memory

10 Clock Reset Generator (CRG)

11 Random Number Generator (RNG)

12 Alternate Function Controller (AFC)

13 External Interrupt (EXTI)

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Summary of Contents for Wiznet W7500