Uart1 Registers(Base Address: 0X4000_D000); Uart1Dr (Uart1 Data Register); Uart1Rsr/Ecr (Uart1 Receive Status Register/Error Clear Register) - Wiznet W7500 Reference Manual

22.6

UART1 Registers(Base address: 0x4000_D000)

22.6.1

UART1DR (UART1 Data Register)

Address offset: 0x000
Reset value: 0x0000_0000
The UART1DR is the data register.
The write operation initiates transmission from the UART. The data is prefixed with a start
bit, appended with the appropriate parity bit(if parity is enabled), and a stop bit. The
resultant word is then transmitted.
The received data byte is read by performing reads from the UARTDR register along with the
corresponding status information.
31 30 29 28
res res res res
15 14 13 12
res res res res
[11] OE – Overrun error
0: data is empty
1: data is received and the receive FIFO is already full.
[10] BE – Break error
1: if a break condition was detected, indicating that the received data input was
held LOW of longer than a full-word transmission time(defined as start, data, parity
and stop bits)
[9] PE – Parity error
1: it indicates that the parity of the received, it indicates that the parity of the
received data character does not match the parity that the EPS and SPS bits in the
line control register, UARTLCR_H
[8] FE – Framing error
1: it indicates that the received
[7:0] DATA – Receive (READ)/Transmit (WRITE) data
22.6.2 UART1RSR/ECR (UART1 Receive Status Register/Error
Clear Register)
Address offset: 0x004
Reset value: 0x0000_0000
The UART1RSR/ECR is the receive status register/error clear register.
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
11 10 9 8
OE BE PE FE
R R R R
23 22 21 20
res res res res
7 6 5 4
19 18 17
res res res
3 2 1
DATA
R/W
462 / 512
16
res
0