Data Validity; Figure 46. I2C Block Diagram; Figure 47. Data Validity - Wiznet W7500 Reference Manual

interface is connected to the ��
connected with a standard (up to 100 KHz), Fast mode (up to 400 KHz) ��
I2C Interrupt
PCLK
SDA is the bi- directions serial data line and SCL is the bi-directions serial clock line. The bus
is considered idle when both lines are high. Every transaction on the ��
long, consisting of eight data bits and a single acknowledge bit and data must be transferred
MSB first.
21.3.1

Data validity

The data on the SDA line must be stable during the HIGH period of the SCL. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW (Figure
47). One clock pulse is generated for each data bit transferred.
SDA
SCL
W7500 Datasheet Version1.0.0
2
bus by a data pin (SDA) and by a Clock pin (SCL). It can be
I2C
APB
interface
Register
Prescale
Block

Figure 46. I2C block diagram

Data line
Stable

Figure 47. Data Validity

DATA
I2C clk
I2C clk
generator
Change of
data allowed
2
bus.
SDA_OEn
I2C
Core
SCL_OEn
2
bus is nine bits
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