Wiznet W7500 Reference Manual page 13

16.4.4 DMA channel alternate control data base pointer register
(DMA_ALT_CTRL_BASE_PTR) .......................................................................... 273
16.4.5 DMA channel wait on request status register (DMA_WAITONREQ_STATUS)
274
16.4.6 DMA channel software request register (DMA_CHNL_SW_REQUEST) ..... 274
16.4.7 DMA channel useburst set register (DMA_CHNL_USEBURST_SET) ......... 275
16.4.8 DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) ...... 276
16.4.9 DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ... 276
16.4.10 DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR) 277
16.4.11 DMA channel enable set register (DMA_CHNL_ENABLE_SET) ............... 277
16.4.12 DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) ............ 278
16.4.13 DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) 278
16.4.14 DMA channel primary-alternate clear register (DMA_CHNL_PRI_ALT _CLR)
279
16.4.15 DMA channel priority set register (DMA_CHNL_PRIORITY_SET) ............ 280
16.4.16 DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) ......... 280
16.4.17 DMA bus error clear register (DMA_ERR_CLR) ................................ 281
16.5 Register map ............................................................................... 282
17 Analog-to-digital converter (ADC) ............................................................... 283
17.1 Introduction ................................................................................ 283
17.2 Features .................................................................................... 283
17.3 Functional description ................................................................... 284
17.3.1 Operation ADC with non-interrupt .............................................. 284
17.3.2 Operation ADC with interrupt ................................................... 286
17.4 Registers (Base address : 0x4100_0000) ............................................... 286
17.4.1 ADC control register (ADC_CTR) ................................................ 286
17.4.2 ADC channel select register (ADC_CHSEL) .................................... 287
17.4.3 ADC start register (ADC_START) ................................................. 288
17.4.4 ADC conversion data register (ADC_DATA) .................................... 288
17.4.5 ADC Interrupt register (ADC_INT) ............................................... 288
17.4.6 ADC Interrupt Clear register (ADC_INTCLR) .................................. 289
17.5 Register map ............................................................................... 290
18 Pulse-Width Modulation (PWM) ................................................................... 291
18.1 Introduction ................................................................................ 291
18.2 Features .................................................................................... 291
18.3 Functional description ................................................................... 292
18.3.1 Timer/Counter control ........................................................... 292
18.3.2 Timer/Counter ..................................................................... 292
18.3.3 PWM mode .......................................................................... 296
W7500 Datasheet Version1.0.0
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