Wiznet W7500 Reference Manual page 22

23.2 Features .................................................................................... 476
23.3 Functional description ................................................................... 477
23.3.1 Clock prescaler .................................................................... 477
23.3.2 Transmit FIFO ...................................................................... 477
23.3.3 Receive FIFO ........................................................................ 478
23.3.4 Interrupt generation logic ....................................................... 478
23.3.5 DMA interface ...................................................................... 478
23.3.6 Interface reset ..................................................................... 480
23.3.7 Configuring the SSP ............................................................... 480
23.3.8 Enable PrimeCell SSP operation ................................................. 481
23.3.9 Clock ratios ......................................................................... 481
23.3.10 Programming the SSPCR0 Control Register .................................... 482
23.3.11 Programming the SSPCR1 Control Register .................................... 482
23.3.12 Frame format ...................................................................... 483
23.3.13 Texas Instruments synchronous serial frame format ........................ 484
23.3.14 Motorola SPI frame format ....................................................... 485
23.3.15 National Semiconductor Microwire frame format ........................... 491
23.3.16 Master and Slave configurations ................................................ 493
23.3.17 SSP Flow chart ..................................................................... 494
23.4 SSP0 Registers (Base Address : 0x4000_A000) ........................................ 496
23.4.1 SSP0 Control register 0 (SSP0CR0) .............................................. 496
23.4.2 SSP0 Control register 1 (SSP0CR1) .............................................. 497
23.4.3 SSP0 Data register (SSP0DR) ..................................................... 497
23.4.4 SSP0 Status register (SSP0SR) ................................................... 498
23.4.5 SSP0 Clock prescale register (SSP0CPSR) ...................................... 499
23.4.6 SSP0 Interrupt mask set or clear register (SSP0IMSC) ....................... 499
23.4.7 SSP0 Raw interrupt status register (SSP0RIS) ................................. 500
23.4.8 SSP0 Masked interrupt status register, (SSP0MIS) ............................ 500
23.4.9 SSP0 Interrupt clear register (SSP0ICR) ........................................ 501
23.4.10 SSP0 DMA control register, (SSP0DMACR) ...................................... 501
23.5 Register map ............................................................................... 503
23.6 SSP1 Registers (Base Address : 0x4000_B000) ........................................ 504
23.6.1 SSP1 Control register 0 (SSP1CR0) .............................................. 504
23.6.2 SSP1 Control register 1 (SSP1CR1) .............................................. 505
23.6.3 SSP1 Data register (SSP1DR) ..................................................... 506
23.6.4 SSP1 Status register (SSP1SR) ................................................... 506
23.6.5 SSP1 Clock prescale register (SSP1CPSR) ...................................... 507
23.6.6 SSP1 Interrupt mask set or clear register (SSP1IMSC) ....................... 507
23.6.7 SSP1 Raw interrupt status register (SSP1RIS) ................................. 508
W7500 Datasheet Version1.0.0
22 / 512