Uart1Lcr_H (Uart1 Line Control Register) - Wiznet W7500 Reference Manual

[5:0] BAUD DIVFRAC – The fractional baud rate divisor.
These bits are cleared to 0 on reset
The baud rate divisor is calculated as follows:
Baud rate divisor BAUDDIV = (��
Where, ��
�� �� ������
The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD
DIVFRAC).
Example 1
If the required baud rate is 115200 and UARTCLK = 8MHz then:
Baud rate divisor = (8
This means BRD
��
(Therefore, UART1IBRD = 4)
Therefore, UART1FBRD = inerger[ ( 34
Generated baud rate divider
Generated baud rate = (8
Error = ( 5 8
When UartCLK = 8MHz
Integer divisor
0x2
0x4
0x6
0x8
0x22
22.6.7

UART1LCR_H (UART1 Line Control Register)

Address offset: 0x002C
Reset value: 0x00
The UART1LCR_H register is the line control register. This register accesses bits 29 to 22 of
the UART line control register, UART1LCR.
31 30 29 28
res res res res
15 14 13 12
W7500 Datasheet Version1.0.0
is the UART reference clock frequency.
6
)/( 6 5
= 4 and BRD = 0.340278
��
UART IBRD
6
)/( 6
5 )/( 5 )
Fractional Required bit
divisor
0x0B
0x16
0x21
0x2C
0x2E
27 26 25
res res res
11 10 9
/( 6
�� �� ������
) 4.340278
64 )
78 5] = 22
(UART FBRD/64) = 4.34375
4 34375) = 115107.914
= -0.07861%
Generated bit
rate(bps) rate(bps)
230400 2.171875
115200 4.34375
76800 6.515625
57600 8.6875
14400 34.71875
24 23 22
res res res res
8 7 6
�������� ��������))
Error%
-0.07994
-0.07994
-0.07994
-0.07994
0.010001
21 20 19 18
res res res
5 4 3 2
466 / 512
17 16
res res
1 0