Figure 69 Motorola Spi Frame Format, Single Transfer, With Spo=0 And Sph=0; Figure 70 Motorola Spi Frame Format, Continuous Transfers, With Spo=0 And Sph=0 - Wiznet W7500 Reference Manual

SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPRXD
nSSPOE
SSPTXD

Figure 69 Motorola SPI frame format, single transfer, with SPO=0 and SPH=0

Figure 70 shows a continuous transmission signal sequence for Motorola SPI frame format
with SPO=0, SPH=0.
SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPTXD/
LSB
SSPRXD
nSSPOE (=0)

Figure 70 Motorola SPI frame format, continuous transfers, with SPO=0 and SPH=0

In this configuration, during idle periods:
• the SSPCLKOUT signal is forced LOW
• the SSPFSSOUT signal is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance
• when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW,
enabling the SSPCLKOUT pad, active-LOW enable
• when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH,
disabling the SSPCLKOUT pad, active-LOW enable.
If the PrimeCell SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSPFSSOUT master signal being driven LOW. This causes the
slave data to be enabled onto the SSPRXD input line of the master. The nSSPOE line is driven
LOW, enabling the master SSPTXD output pad.
W7500 Datasheet Version1.0.0
MSB
4 to 16 bits
MSB MSB
MSB
4 to 16 bits
LSB LSB
LSB LSB
LSB LSB MSB
486 / 512
Q