Uart1Ilpr (Uart1 Irda Low-Power Counter Register) - Wiznet W7500 Reference Manual

This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when transmit holding register is empty.
1: The bit is set when transmit FIFO is empty
[6] RXFF – Receive FIFO full
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when the receive holding register is full
1: The bit is set when the receive FIFO is full
[5] TXFF – Transmit FIFO full
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when transmit holding register is full.
1: The bit is set when transmit FIFO is full.
[4] RXFE – Receive FIFO empty
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when the receive holding register is empty.
1: The bit is set when the receive FIFO is empty.
[3] BUSY – UART busy
1: the UART is busy transmitting data
[2] DCD – Data carrier detect
This bit is the complement of the UART data carrier detect, UART1DCD, status
input
1: The bit is the complement of the UART data carrier detect
[1] DSR – Data set ready
This bit is the complement of the UART data set ready, UART1DSR, status input
1: The bit is the complement of the UART data set ready
[0] CTS – Clear to send
This bit is the complement of the UART clear to send, UART1CTS, status input
1: The bit is the complement of the UART clear to send
22.6.4

UART1ILPR (UART1 IrDA Low-Power Counter Register)

Address offset: 0x0020
Reset value: 0x00
The UARTILPR Register is the IrDA low-power counter register
31 30 29 28
res res res res
W7500 Datasheet Version1.0.0
27 26 25 24
res res res res
23 22 21 20
res res res res
19 18 17 16
res res res res
464 / 512