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18.7
Register map
The following Table 22 summarizes the PWM Channel-1 registers.
Offset
Register
PWMCH1IR
0x00
reset value
PWMCH1IER
0x04
reset value
PWMCH1ICR
0x08
reset value
PWMCH1TCR
0x0C
0
0
0
reset value
PWMCH1PCR
0x10
reset value
PWMCH1PR
0x14
reset value
PWMCH1MR
0x18
reset value
0
0
0
PWMCH1LR
0x1C
1
1
1
reset value
PWMCH1UDMR
0x20
reset value
PWMCH1TCMR
0x24
reset value
PWMCH1PEEER
0x28
reset value
PWMCH1CMR
0x2C
reset value
PWMCH1CR
0x30
reset value
0
0
0
PWMCH1PDMR
0x34
reset value
PWMCH1DZER
0x38
reset value
PWMCH1DZCR
0x3C
reset value
W7500 Datasheet Version1.0.0
Table 22 PWM channel 1 register map and reset values
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
TCR
0
0
0
0
0
0
0
0
0
0
0
MR
0
0
0
0
0
0
0
0
0
0
0
LR
1
1
1
1
1
1
1
1
1
1
1
CR
0
0
0
0
0
0
0
0
0
0
0
DZC
0
0
0
0
비고
Channel-1 interrupt register
0
0
0
Channel-1 interrupt enable register
0
0
0
Channel-1 interrupt clear register
Write only register
Channel-1 Timer/Counter Register
0
0
0
0
0
0
Channel-1 Prescale Counter
PCR
Register
0
0
0
0
0
0
PR
Channel-1 Prescale Register
0
0
0
0
0
0
Channel-1 Match Register
0
0
0
0
0
0
Channel-1 Limit Register
1
1
1
1
1
1
Channel-1 Up-Down Mode Register
0
Channel-1 Timer/Counter Mode
TCM
Register
0
0
Channel-1 PWM output Enable and
PEEE
External input Enable Register
0
0
Channel-1 Capture Mode Register
0
Channel-1 Capture Register
0
0
0
0
0
0
Channel-1 Periodic Mode Register
0
Channel-1 Dead Zone Enable
Register
0
Channel-1 Dead Zone Counter
Register
0
0
0
0
0
0
319 / 512
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