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configured as a slave, enabling or disabling of the PrimeCell SSP SSPTXD signal is provided
through the SSPCR1 slave mode SSPTXD output disable bit, SOD. You can use this in some
multi-slave environments where masters might parallel broadcast.
Set the Synchronous Serial Port Enable (SSE) bit to 1 to enable the operation of the PrimeCell
SSP.
Bit rate generation
The serial bit rate is derived by dividing down the input clock SSPCLK. The clock is first
divided by an even prescale value CPSDVSR in the range of 2-254, and is programmed in
SSPCPSR. The clock is divided again by a value in the range of 1-256, that is 1 + SCR, where
SCR is the value programmed in SSPCR0.
The following equation defines the frequency of the output signal bit clock, SSPCLKOUT:
F
SSPCLKOUT
For example, if SSPCLK is 3.6864MHz, and CPSDVSR = 2, then SSPCLKOUT has a
frequency range of 7.2kHz-1.8432MHz.
23.3.12
Frame format
Each data frame is between 4-16 bits long depending on the size of data programmed and is
transmitted starting with the MSB. Users can select the following basic frame types:
• Texas Instruments synchronous serial
• Motorola SPI
• National Semiconductor Microwire.
For all formats, the serial clock SSPCLKOUT is held inactive while the PrimeCell SSP is idle
and transitions at the programmed frequency only during active transmission or reception of
data. The idle state of SSPCLKOUT is utilized to provide a receive timeout indication that
occurs when the receive FIFO still contains data after a timeout period.
For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame
SSPFSSOUT pin is active-LOW and is asserted and pulled-down during the entire transmission
of the frame.
W7500 Datasheet Version1.0.0
F
SSPCLK
CPSDVR
(
SCR)
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