Figure 71 Motorola Spi Frame Format, Single And Continuous Transfers, With Spo=0 And; Sph=1 - Wiznet W7500 Reference Manual

One half SSPCLKOUT period later, valid master data is transferred to the SSPTXD pin. Now
that both the master and slave data have been set, the SSPCLKOUT master clock pin goes
HIGH after one additional half SSPCLKOUT period.
The data is now captured on the rising and propagated on the falling edges of the
SSPCLKOUT signal.
In the case of a single word transmission after all bits of the data word have been
transferred, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period
after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must
be pulsed HIGH between each data word transfer. This is because the slave select pin freezes
the data in its serial peripheral register and does not permit it to be altered if the SPH bit is
logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave device
between each data transfer to enable the serial peripheral data write. On completion of the
continuous transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period
after the last bit has been captured.
Figure 71 shows the transfer signal sequence for Motorola SPI format with SPO=0, SPH=1, and
it covers both single and continuous transfers.
SSPCLKOUT/
SSPCLKIN
SSPFSSOUT/
SSPFSSIN
SSPRXD
nSSPOE
SSPTXD
Figure 71 Motorola SPI frame format, single and continuous transfers, with SPO=0 and SPH=1
In this configuration, during idle periods:
• the SSPCLKOUT signal is forced LOW
• The SSPFSSOUT signal is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
W7500 Datasheet Version1.0.0
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