Uart0Ilpr (Uart0 Irda Low-Power Counter Register) - Wiznet W7500 Reference Manual

[7] TXFE – Transmit FIFO empty
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when transmit holding register is empty.
1: The bit is set when transmit FIFO is empty
[6] RXFF – Receive FIFO full
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when the receive holding register is full
1: The bit is set when the receive FIFO is full
[5] TXFF – Transmit FIFO full
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when transmit holding register is full.
1: The bit is set when transmit FIFO is full.
[4] RXFE – Receive FIFO empty
This bit depends on the state of the FEN bit in the line control register,
UARTLCR_H.
0: The bit is set when the receive holding register is empty.
1: The bit is set when the receive FIFO is empty.
[3] BUSY – UART busy
1: the UART is busy transmitting data
[2] DCD – Data carrier detect
This bit is the complement of the UART data carrier detect, UART0DCD, status
input
1: The bit is the complement of the UART data carrier detect
[1] DSR – Data set ready
This bit is the complement of the UART data set ready, UART0DSR, status input
1: The bit is the complement of the UART data set ready
[0] CTS – Clear to send
This bit is the complement of the UART clear to send, UART0CTS, status input
1: The bit is the complement of the UART clear to send
22.4.4

UART0ILPR (UART0 IrDA Low-Power Counter Register)

Address offset: 0x0020
Reset value: 0x00
The UARTILPR Register is the IrDA low-power counter register
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