Pwm Channel-3 Registers (Base Address : 0X4000_5300); Channel-3 Interrupt Register(Pwmch3Ir); Channel-3 Interrupt Enable Register(Pwmch3Ier) - Wiznet W7500 Reference Manual

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PWM Channel-3 Registers (Base address : 0x4000_5300)

Base address : 0x4000_5300

Address offset : 0x00

Reset value : 0x0000_0000

[0] MI – Match Interrupt

This bit is set by hardware and cleared by interrupt clear register.

O : Match interrupt does not occur.

1 : Match interrupt occurs.

[1] OI – Overflow Interrupt

This bit is set by hardware and cleared by interrupt clear register.

O : Overflow interrupt does not occur.

1 : Overflow interrupt occurs.

[2] CI – Capture Interrupt

This bit is set by hardware and cleared by interrupt clear register.

O : Capture interrupt does not occur.

1 : Capture interrupt occurs.

Base address : 0x4000_5300

Address offset : 0x04

Reset value : 0x0000_0000

W7500 Datasheet Version1.0.0