Exception Processing; Exception Vectors; Table 2-5. M68000 Exception Vector Assignment - Motorola MC68302 User Manual

MC68000/MC68008 Core
Once the processor is in the user state and executing instructions, only exception process-
ing can change the privilege state. During exception processing, the current state of the S
bit in the SR is saved and the S bit is asserted, putting the processor in the supervisor state.
Therefore, when instruction execution resumes at the address specified to process the ex-
ception, the processor is in the supervisor privilege state. The transition from the supervisor
to user state can be accomplished by any of four instructions: return from exception (RTE),
move to status register (MOVE to SR), AND immediate to status register (ANDI to SR), and
exclusive OR immediate to status register (EORI to SR).

2.4 EXCEPTION PROCESSING

The processing of an exception occurs in four steps, with variations for different exception
causes. During the first step, a temporary copy of the SR is made, and the SR is set for ex-
ception processing. During the second step, the exception vector is determined; during the
third step, the current processor context is saved. During the fourth step, a new context is
obtained, and the processor switches to instruction processing.

2.4.1 Exception Vectors

Exception vectors are memory locations from which the processor fetches the address of a
routine to handle that exception. All exception vectors are two words long except for the re-
set vector, which is four words. All exception vectors lie in the supervisor data space except
for the reset vector, which is in the supervisor program space. A vector number is an 8-bit
number which, when multiplied by four, gives the offset of the exception vector. Vector num-
bers are generated internally or externally, depending on the cause of the exception. In the
case of interrupts, during the interrupt acknowledge bus cycle, a peripheral may provide an
8-bit vector number to the processor on data bus lines D7–D0. Alternatively, the peripheral
may assert autovector (AVEC) instead of data transfer acknowledge (DTACK) to request an
autovector for that priority level of interrupt. The exception vector assignments for the
M68000 processor are shown in Table 2-5.

Table 2-5. M68000 Exception Vector Assignment

Vector
Number
0
1
2
3
4
5
6
7
8
9
10
2-8
Address
Decimal Space
Hex
0 000
4 004
8 008
12 00C
16 010
20 014
24 018
28 01C
32 020
36 024
40 028
MC68302 USER'S MANUAL
Assignment
SP
Reset: Initial SSP
2
SP
Reset: Initial PC
SD Bus Error
SD Address Error
SD Illegal Instruction
SD Zero Divide
SD CHK Instruction
SD TRAPV Instruction
SD Privilege Violation
SD Trace
SD Line 1010 Emulator
2
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