Figure 5-2 Program Controller Programming Model; Program Counter; Instruction Latch And Instruction Decoder; Interrupt Control Unit - Motorola DSP56800 Manual

15
PC
Program
Counter
15
DO Loop Stack (HWS)
5.1.1

Program Counter

The program counter (PC) is a 16-bit register that contains the address of the next location to be fetched
from program memory space. The PC may point to instructions, data operands, or addresses of operands.
Reference to this register is always implicit and is implied by most instructions. This special-purpose
address register is stacked when hardware DO looping is initiated (on the hardware stack), when a jump to
a subroutine is performed (on the software stack), and when interrupts occur (on the software stack).
5.1.2

Instruction Latch and Instruction Decoder

The instruction latch is a 16-bit internal register used to hold all instruction opcodes fetched from memory.
The instruction decoder, in turn, uses the contents of the instruction latch to generate all control signals
necessary for pipeline control—for normal instruction fetches, jumps, branches, and hardware looping.
5.1.3

Interrupt Control Unit

The interrupt control unit receives all interrupt requests, arbitrates among them, and then checks the
highest-priority interrupt request against the interrupt mask bits for the DSP core (I1 and I0 in the SR). If
the requesting interrupt has higher priority than the current priority level of the DSP core, then exception
processing begins. When exception processing begins, the interrupt control unit provides the address of the
interrupt vector for interrupts generated on the DSP core, whereas the peripherals generate the vector
address for interrupts generated by an on-chip peripheral.
Interrupts have a simple priority structure with levels zero or one. Level 0 is the lowest interrupt priority
level (IPL) and is maskable. Level 1 is the highest level and is not maskable. Two interrupt mask bits in the
SR reflect the current IPL of the DSP core and indicate the level needed for an interrupt source to interrupt
the processor.
The DSP56800 core provides support for internal (on-chip) peripheral interrupts and two external interrupt
sources, IRQA and IRQB. The interrupt control unit arbitrates between interrupt requests generated
externally and by the on-chip peripherals.
Asserting the reset pin causes the DSP core to enter the reset processing state. This has higher priority and
overrides any activity in the interrupt control unit and the exception processing state.
Program Controller
0 15
MR
Status Register (SR)
12
0
Loop Counter
Figure 5-2. Program Controller Programming Model
Program Controller
Architecture and Programming Model
8 7 0 15
CCR
Operating Mode
0
15
LC
0
OMR
Register
0
LA
Loop Address
AA0009
5-3