ST STM32F413 Reference Manual page 165

RM0430
6.3.22 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0317 F9F3h
Access: no wait state, word, half-word and byte access.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
SYSC
SPI1
EXTIT SPI4LP
FG
LPEN EN
LPEN
LPEN
rw rw rw rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 DFSDM2LPEN: DFSDM2 clock enable during Sleep mode
Bit 24 DFSDM1LPEN: DFSDM1 clock enable during Sleep mode
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI1LPEN: SAI1 clock enable during Sleep mode
Bit 21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
27 26 25
DFSDM2
Res. Res.
LPEN
11 10 9
SDIO
Res. Res.
LPEN
rw
This bit is set and cleared by software
0: DFSDM2 clock disabled during Sleep mode
1: DFSDM2 clock enabled during Sleep mode
This bit is set and cleared by software
0: DFSDM1 clock disabled during Sleep mode
1: DFSDM1 clock enabled during Sleep mode
This bit is set and cleared by software
0: SAI1 clock disabled during Sleep mode
1: SAI1 clock enabled during Sleep mode
This bit is set and cleared by software
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Reset and clock control (RCC) for STM32F413/423
24 23 22
DFSDM1 SAI1
Res.
LPEN IPEN
rw
8 7 6
ADC1
UART10 UART9
LPEN LPEN
LPEN
rw rw rw
DocID029473 Rev 3
21 20 19 18
SPI5 TIM11
Res. Res.
LPEN LPEN
rw rw
5 4 3 2
USART6 USART1
Res. Res.
LPEN LPEN
rw rw
17 16
TIM10 TIM9
LPEN LPEN
rw rw
1 0
TIM8 TIM1
LPEN LPEN
rw rw
165/1284
180