ST STM32F413 Reference Manual page 162

Reset and clock control (RCC) for STM32F413/423
6.3.21 RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0xFFFF CFFF
Access: no wait state, word, half-word and byte access.
31 30 29 28
PWR
UART8 UART7 DACLP
LPEN LPEN LPEN
LPEN
rw
15 14 13 12
SPI3 SPI2
Res. Res.
LPEN LPEN
rw rw
Bit 31 UART8LPEN: UART8 clock enable during Sleep mode
Set and cleared by software.
0: UART8 clock disabled during Sleep mode
1: UART8 clock enabled during Sleep mode
Bit 30 UART7LPEN: UART7 clock enable during Sleep mode
Set and cleared by software.
0: UART7 clock disabled during Sleep mode
1: UART7 clock enabled during Sleep mode
Bit 29 DACLPEN: DAC clock enable during Sleep mode
Set and cleared by software.
0: DAC clock disabled during Sleep mode
1: DAC clock enabled during Sleep mode
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
Set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bit 27 CAN3LPEN: CAN3 clock enable during Sleep mode
Set and cleared by software.
0: CAN3 clock disabled during Sleep mode
1: CAN3 clock enabled during Sleep mode
Bit 26 CAN2LPEN: CAN2 clock enable during Sleep mode
Set and cleared by software.
0: CAN2 clock disabled during Sleep mode
1: CAN2 clock enabled during Sleep mode
Bit 25 CAN1LPEN: CAN1 clock enable during Sleep mode
Set and cleared by software.
0: CAN1 clock disabled during Sleep mode
1: CAN1 clock enabled during Sleep mode
Bit 24 I2CFMP1LPEN: I2CFMP1 clock enable during Sleep mode
Set and cleared by software.
0: I2CFMP1 clock disabled during Sleep mode
1: I2CFMP1 clock enabled during Sleep mode
162/1284
27 26 25
CAN2 CAN1
CAN3
LPEN
LPEN LPEN
rw rw
11 10 9
WWDG RTCAPB
IPTIMER1
LPEN
LPEN LPEN
rw rw rw
DocID029473 Rev 3
24 23 22 21
I2C3 I2C2 I2C1
I2C4
LPEN
LPEN LPEN LPEN
rw rw rw rw
8 7 6 5
TIM14 TIM13 TIM12 TIM7
LPEN LPEN LPEN LPEN
rw rw rw rw
20 19 18
USART3 USART2
UART5 UART4
LPEN LPEN
LPEN LPEN
rw
4 3 2
TIM6 TIM5 TIM4 TIM3
LPEN LPEN LPEN LPEN
rw rw rw
RM0430
17 16
Res.
rw
1 0
TIM2
LPEN
rw rw