ST STM32F413 Reference Manual page 154

Reset and clock control (RCC) for STM32F413/423
6.3.16 RCC APB2 peripheral clock enable register
(RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 8000
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res.
15 14 13
EXTIT SYSCFG
SPI4EN
EN EN
rw rw rw
Bits 31:26 Reserved, always read as 0.
Bit 25 DFSDM2EN: DFSDM2 clock enable
Bit 24 DFSDM1EN: DFSDM1 clock enable
Bit 23 Reserved, always read as 0.
Bit 22 SAI1EN:SAI 1 clock enable
Bit 21 Reserved, always read as 0.
Bit 20 SPI5EN:SPI5 clock enable
Bit 19 Reserved, always read as 0.
Bit 18 TIM11EN: TIM11 clock enable
Bit 17 TIM10EN: TIM10 clock enable
154/1284
28 27 26 25
DFSDM2
Res. Res. Res.
EN
12 11 10 9
SPI1 SDIO
Res. Res.
EN EN
rw rw
Set and cleared by software
0: DFSDM2 clock disabled
1: DFSDM2 clock enabled
Set and cleared by software
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Set and cleared by software
0: SAI 1 clock disabled
1: SAI 1 clock enabled
Set and cleared by software
0: SPI5 clock disabled
1: SPI5 clock enabled
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
24 23 22
DFSDM1 SAI1
Res.
EN EN
rw
8 7 6
ADC1
UART10 UART9
EN EN
EN
rw rw rw
DocID029473 Rev 3
21 20 19
TIM11
SPI5
Res. Res.
EN
rw
5 4 3
USART6 USART1
Res. Res.
EN EN
rw rw
RM0430
18 17 16
TIM10 TIM9
EN EN EN
rw rw rw
2 1 0
TIM8 TIM1
EN EN
rw rw