Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr) - ST STM32F413 Reference Manual

Reset and clock control (RCC) for STM32F413/423
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8RST: TIM8 reset
Bit 0 TIM1RST: TIM1 reset
6.3.11

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. CRCEN
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
Set and reset by software.
0: IO port H clock disabled
1: IO port H clock enabled
146/1284
Set and cleared by software.
0: does not reset TIM8
1: resets TIM8
Set and cleared by software.
0: does not reset TIM1
1: resets TIM1
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
24 23 22
Res. Res. DMA2EN DMA1EN
rw
8 7 6
GPIOH GPIOG
Res.
EN EN
rw rw
DocID029473 Rev 3
21 20 19
Res. Res.
rw
5 4 3
GPIOF GPIOE GPIOD
EN EN EN
rw rw rw
RM0430
18 17 16
Res. Res. Res.
2 1 0
GPIOC GPIOB GPIOA
EN EN EN
rw rw rw