ST STM32F413 Reference Manual page 157

RM0430
6.3.17 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x0063 90FF
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res.
15 14 13
FLITF
Res. Res.
LPEN LPEN
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 SRAM2LPEN: SRAM2interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM2 interface clock disabled during Sleep mode
1: SRAM2 interface clock enabled during Sleep mode
Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
Bits 11:8 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
CRC
Res. Res. Res.
rw
DocID029473 Rev 3
Reset and clock control (RCC) for STM32F413/423
24 23 22 21
DMA2 DMA1
Res. Res.
LPEN LPEN
rw rw
8 7 6 5
GPIOH GPIOG GPIOF
Res.
LPEN LPEN LPEN
rw rw rw
20 19 18
SRAM2
Res. Res. Res.
LPEN
4 3 2
GPIOE GPIOD GPIOC GPIOB
LPEN LPEN LPEN LPEN
rw rw rw
17 16
SRAM1
LPEN
rw
1 0
GPIOA
LPEN
rw rw
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