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Reset and clock control (RCC) for STM32F413/423
6.3.12
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F413xx
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bit 6 RNGEN: RNG clock enable
Set and cleared by software.
0: RNG clock disabled
1: RNG clock enabled
Bits 5:0 Reserved, always read as 0.
148/1284
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
DocID029473 Rev 3
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
OTGFS
RNG
Res.
Res.
EN
EN
rw
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
Res.
RM0430
16
Res.
0
Res.
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