Rcc Clock Control & Status Register (Rcc_Csr) - ST STM32F413 Reference Manual

RM0430
Bit 2 LSEBYP: External low-speed oscillator bypass
Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the LSE clock is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE clock not ready
1: LSE clock ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: LSE clock OFF
1: LSE clock ON
6.3.24 RCC clock control & status register (RCC_CSR)
Address offset: 0x74
Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.
Access: 0
Wait states are inserted in case of successive accesses to this register.
31 30 29
LPWR WWDG IWDG SFT
RSTF RSTF RSTF RSTF
r r r
15 14 13
Res. Res. Res. Res.
Bit 31 LPWRRSTF: Low-power reset flag
Bit 30 WWDGRSTF: Window watchdog reset flag
Bit 29 IWDGRSTF: Independent watchdog reset flag
wait state 3, word, half-word and byte access
≤ ≤
28 27 26 25
POR PIN
BORRS
TF
RSTF RSTF
r r r r
12 11 10 9
Res. Res. Res.
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
reset.
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Set by hardware when an independent watchdog reset from V
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Reset and clock control (RCC) for STM32F413/423
24 23 22
RMVF Res. Res.
rt_w
8 7 6
Res. Res. Res.
DocID029473 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
Low-power management
domain occurs.
DD
17 16
Res. Res.
1 0
LSIRDY LSION
r rw
169/1284
180