For Stm32F423Xx - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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6.3.13

RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 OTGFSEN: USB OTG FS clock enable

Set and cleared by software.

0: USB OTG FS clock disabled

1: USB OTG FS clock enabled

Bit 6 RNGEN: RNG clock enable

Set and cleared by software.

0: RNG clock disabled

1: RNG clock enabled

Bit 5 Reserved, always read as 0.

Bit 4 CRYPEN: CRYP clock enable

Set and reset by software.

0: CRYP clock disabled

1: CRYP clock enabled

Bits 3:0 Reserved, always read as 0.

DocID029473 Rev 3

Reset and clock control (RCC) for STM32F413/423