Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr) - ST STM32F413 Reference Manual

RM0430
6.3.25

RCC spread spectrum clock generation register (RCC_SSCGR)

Address offset: 0x80
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The spread spectrum clock generation is available only for the main PLL.
The RCC_SSCGR register must be written either before the main PLL is enabled or after
the main PLL disabled.
Note: For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to
the "Electrical characteristics" section in your device datasheet.
31 30 29
SPREAD
SSCG
Res.
EN
SEL
rw rw
15 14 13
INCSTEP[2:0]
rw rw rw
Bit 31 SSCGEN: Spread spectrum modulation enable
Bit 30 SPREADSEL: Spread Select
Bits 29:28 Reserved, must be kept at reset value.
Bits 27:13 INCSTEP[14:0]: Incrementation step
Bits 12:0 MODPER[11:0]: Modulation period
28 27 26 25
Res.
rw rw rw
12 11 10
rw rw rw rw
Set and cleared by software.
0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)
1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)
Set and cleared by software.
To write before to set CR[24]=PLLON bit.
0: Center spread
1: Down spread
Set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile amplitude.
Set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile period.
DocID029473 Rev 3
Reset and clock control (RCC) for STM32F413/423
24 23 22
INCSTEP[14:3]
rw rw rw
9 8 7 6
MODPER[11:0]
rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
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