Pci Controller Status Register (Pcicstatus) 0Xd174 - Toshiba TMPR4925 Manual

10.4.43 PCI Controller Status Register (PCICSTATUS)
31
15
Bits Mnemonic Field Name
⎯
31:1 Reserved
0 SERR SERR* Detected
Reserved
Reserved
SERR* Occurred (Initial value: 0, R/W1C)
Indicates that the System Error signal (SERR*) was asserted. This bit is a monitor
status bit that records assertion of the SERR* signal even if the TX4925 is not
accessing PCI.
1: Indicates that the SERR* signal was asserted.
0: Indicates that the SERR* signal was not asserted.
Figure 10.4.43 PCI Controller Status Register
10-72
Chapter 10 PCI Controller
0xD174
1
Description
⎯
16
: Type
: Initial value
0
SERR
R/W1C : Type
0 : Initial value