Register - Toshiba TMPR4925 Manual

5.2

Register

Table 5.2.1 lists the configuration registers.
Reference Offset Address
5.2.1 0xE000
5.2.2 0xE004
5.2.3 0xE008
5.2.4 0xE00C
5.2.5 0xE010
⎯
0xE014
5.2.6 0xE018
⎯
0xE01C
5.2.7 0xE020
5.2.8 0xE024
5.2.9 0xE028
5.2.10 0xE02C
5.2.11 0xE030
⎯
0xE034
Any address not defined in this table is reserved for future use.
Chapter 5 Configuration Register
Table 5.2.1 Configuration Register Map
Size in Bits Mnemonic
32 CCFG
32 REVID
32 PCFG
32 TOEA
32 PDNCTR
⎯
32
32 GARBP
⎯
32
32 TOCNT
32 DRQCTR
32 CLKCTR
32 GARBC
32 RAMP
⎯
32
5-2
Register Name
Chip Configuration Register
Chip Revision ID Register
Pin Configuration Register
Timeout Error Access Address Register
Power Down Control Register
(Reserved)
GBUS Arbiter Priority Register
(Reserved)
Timeout Count Register
DMA Request Control Register
Clock Control Register
GBUS Arbiter Control Register
Register Address Mapping Register
(Reserved)