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Offset Address
Register Size (bit) Register Symbol
SDRAM Controller (SDRAMC)
0x8000
0x8004
0x8008
0x800C
0x8020
0x802C
External Bus Controller (EBUSC)
0x9000
0x9004
0x9008
0x900C
0x9010
0x9014
0x9018
0x901C
0x9020
0x9024
0x9028
0x902c
0x9030
0x9034
0x9038
0x903c
CHI Module (CHI)
0xA800
0xA804
0xA808
0xA80C
0xA810
0xA814
0xA818
0xA81C
0xA820
0xA824
0xA828
0xA82C
0xA830
Table 4.2.2 Internal Registers (1/8)
32
SDCCR0
32
SDCCR1
32
SDCCR2
32
SDCCR3
32
SDCTR
32
SDCCMD
32
EBCCR0
32
EBBAR0
32
EBCCR1
32
EBBAR1
32
EBCCR2
32
EBBAR2
32
EBCCR3
32
EBBAR3
32
EBCCR4
32
EBBAR4
32
EBCCR5
32
EBBAR5
32
EBCCR6
32
EBBAR6
32
EBCCR7
32
EBBAR7
32
CTRL
32
PNTREN
32
RXPTRA
32
RXPTRB
32
TXPTRA
32
TXPTRB
32
CHISIZE
32
RXSTRT
32
TXSTRT
32
HOLD
32
CLOCK
32
CHIINTE
32
CHIINT
4-4
Chapter 4 Address Mapping
Register Name
SDRAM Channel Control Register 0
SDRAM Channel Control Register 1
SDRAM Channel Control Register 2
SDRAM Channel Control Register 3
SDRAM Timing Register
SDRAM Command Register
EBUS Channel Control Register 0
EBUS Base Address Register 0
EBUS Channel Control Register 1
EBUS Base Address Register 1
EBUS Channel Control Register 2
EBUS Base Address Register 2
EBUS Channel Control Register 3
EBUS Base Address Register 3
EBUS Channel Control Register 4
EBUS Base Address Register 4
EBUS Channel Control Register 5
EBUS Base Address Register 5
EBUS Channel Control Register 6
EBUS Base Address Register 6
EBUS Channel Control Register 7
EBUS Base Address Register 7
CHI Control Register
CHI Pointer Enable Register
CHI Receive Pointer A Register
CHI Receive Pointer B Register
CHI Transmit Pointer A Register
CHI Transmit Pointer B Register
CHI Size Register
CHI RX Start Register
CHI TX Start Register
CHI TX/RX Hold Register
CHI Clock Register
CHI Interrupt Enable Register
CHI Interrupt Status Register
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