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9.4.1
SDRAM Channel Control Register (SDCCR0) 0x8000 (ch. 0)
31
15
AM[26:21]
R/W
0x00
Bits
Mnemonic
Field Name
31:21
BA[31:21]
Base Address
20:10
AM[31:21]
Address Mask
9
CE
Channel Enable
8
MT
Memory Type
7
RD
Registered DIMM
⎯
6
Reserved
5:4
RS
Row Size
(SDCCR1) 0x8004 (ch. 1)
(SDCCR2) 0x8008 (ch. 2)
(SDCCR3) 0x800C (ch. 3)
BA
R/W
0x000
10
9
8
CE
MT
RD
R/W
R/W
R/W
0
0
Base Address (Initial value: 0x000, R/W)
Specifies the base address. The upper 11 bits [31:21] of the physical address are
compared to the value of this field.
Address Mask (Initial value: 0x000, R/W)
Sets the valid bits for address comparison according to the base address.
0: Bits of the corresponding BA field are compared.
1: Bits of the corresponding BA field are not compared.
Enable (Initial value: 0, R/W)
Specifies whether to enable a channel.
0: Disable
1: Enable
Memory Type (Initial value: 0, R/W)
Always set to 0.
Registered DIMM (Initial value: 0, R/W)
Specifies whether the SDRAM connected to the channel is Registered memory.
0: Disable Registered memory
1: Enable Registered memory
Note: this bit is always set to "0" (Initial value: 0, R/W)
Row Size (Initial value: 00, R/W)
Specifies the row size.
00: 2048 Rows (11 bits)
01: 4096 Rows (12 bits)
10: 8192 Rows (13 bits)
11: Reserved
Figure 9.4.1 SDRAM Channel Control Register (1/2)
9-13
Chapter 9 SDRAM Controller
21
20
7
6
5
4
RS
Reserved
R/W
R/W
0
0
0
0
Description
16
AM[31:27]
R/W
: Type
: Initial
0x0
value
3
2
1
0
CS
MW
R/W
R/W : Type
: Initial
0
0
0
0
value
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