Toshiba TMPR4925 Manual page 420

14.3.6.4 DMA Operation
When ACLC's REQ latch (refer to Figure 14.3.6 and Figure 14.3.7) needs to read or write
sample-data, it issues a DMA request. When DMAC acknowledges the request by performing
write- or read-access to the ACLC sample-data register, ACLC deasserts the request. Therefore,
the software must properly set up DMAC so that the source or destination points to the
corresponding sample-data register for the DMA channel.
Setup the DMA Channel Control Registers (DMCCRn) in DMAC as follows.
Immediate chain
DMA request polarity
DMA acknowledge polarity
Request sense
Simple chain
Transfer size
Transfer address mode
Note: Use this setting when DMA chain operation is utilized
For a transmission channel, assign the address of ACLC Audio PCM
Output/Surround/Center/LFE/Modem Output Register
(ACAUDO/SURR/CENT/LFE/MODODAT) to the DMAC destination address register
(DMDARn). For a reception channel, assign the address of ACLC Audio input/Modem Input
Register (ACAUDI/MODIDAT) to the DMAC source address register (DMSARn).
When any DMA request is pending, the REQ latch will not deasserted the request until the
corresponding sample-data register is accessed. Just unsetting ACLC Control Enable Register
(ACCTLEN)'s DMA Enable (xxxxDMA) bit corresponding to the DMA will not clear the REQ
latch.
The procedure to continuously push or pull the sample-data stream through the chain DMA
operation follows the DMAC specification. Refer to section 8.3.10 for this respect.
Chapter 14 AC-link Controller
Enable DMCCRn.IMMCHN = 1 [Note]
Low-active DMCCRn.REQPOL = 0
Low-active DMCCRn.ACKPOL = 0
Level-sensitive DMCCRn.EGREQ = 0
Enable DMCCRn.SMPCHN = 1
1 word DMCCRn.XFSZ = 010b
Dual DMCCRn.SNGAD = 0
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