Toshiba TMPR4925 Manual page 258

Chapter 9 SDRAM Controller
SDCLK
SDCS*
ADDR [19:16]
SADDR10
0000 0400
ADDR[14:5]
RAS*
CAS*
WE*
CKE
DQM [3:0]
f 0 f
DATA [31:0]
ACK*/READY*
Figure 9.5.15 Power Down Auto Entry (SDCTR.PDAE=1, SDCTR.ACE=0)
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