0Xb04C (Ch. 2) 0Xb06C (Ch. 3) - Toshiba TMPR4925 Manual

8.4.9 DMA Count Register (DMCNTRn)
31
Reserved
15
Bits Mnemonic Field Name
⎯
31:26 Reserved
25:0 DMCNTR Count
0xB00C (ch. 0)
0xB04C (ch. 2)
26 25
DMCNTR[15:0]
R/W
-
Count Register (Initial value: undefined, R/W)
This register sets the byte count that is transferred by the DMA Channel Register
setting. The value is a 26-bit unsigned data that is decremented only by the size of
the data transferred during a single bus operation.
Refer to "8.3.7.1 Channel Register Settings During Single Address Transfer" and
"8.3.8.1 Channel Register Settings During Dual Address Transfer" for more
information.
Figure 8.4.9 DMA Count Register
8-35
Chapter 8 DMA Controller
0xB02C (ch. 1)
0xB06C (ch. 3)
DMCNTR[25:16]
R/W
-
Description
⎯
16
: Type
: Initial value
0
: Type
: Initial value