Toshiba TMPR4925 Manual page 181

When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to
the Destination Address is divided into multiple 4-byte Single Write transfers, then transfer is
executed.
Only 4, 0 and 4 can be set on Burst Inhibit bit during Burst transfer. When the Burst Inhibit bit
is set, an any multiples of 4 can be set. (Refer to Table 8.3.3)
8.3.8.3 Double Word Byte Swapping
When the Reverse Byte bit (REVBYTE) of the DMA Channel Configuration Register
(DMCCRn) is set, read word data is written after byte swapping is performed. For example, if the
read data is "0x0123_4567", then the data "0x6745_2301" is written.
The Reverse Byte bit can only be set when the REVBYTE column of Table 8.3.3 is set so "0/1"
is indicated.
Chapter 8 DMA Controller
8-13