Toshiba TMPR4925 Manual page 285

Section Address Bit Width
10.4.39 0xD158 32
10.4.40 0xD160 32
10.4.41 0xD168 32
10.4.42 0xD170 32
10.4.43 0xD174 32
10.4.44 0xD178 32
10.4.45 0xD180 32
10.4.46 0xD184 32
10.4.47 0xD188 32
10.4.48 0xD18C 32
10.4.49 0xD190 32
10.4.50 0xD194 32
10.4.51 0xD198 32
10.4.52 0xD19C 32
10.4.53 0xD1A0 32
10.4.54 0xD1A4 32
⎯ ⎯
0xD1B0
⎯ ⎯
0xD1B8
⎯ ⎯
0xD1C0
10.4.55 0xD1C8 32
10.4.56 0xD1CC 32
10.4.57 0xD1E0 32
10.4.58 0xD1E4 32
10.4.59 0xD1E8 32
10.4.60 0xD1EC 32
10.4.61 0xD200 32
10.4.62 0xD204 32
10.4.63 0xD208 32
10.4.64 0xD20C 32
10.4.65 0xD210 32
10.4.66 0xD214 32
Table 10.4.1 PCI Controller Control Register (2/2)
Mnemonic
G2PM1PBASE G2P Memory Space 1 PCI Base Address Register
G2PM2PBASE G2P Memory Space 2 PCI Base Address Register
G2PIOPBASE G2P I/O Space PCI Base Address Register
PCICCFG PCI Controller Configuration Register
PCICSTATUS PCI Controller Status Register
PCICMASK PCI Controller Interrupt Mask Register
P2GM0GBASE P2G Memory Space 0 G-Bus Base Address Register
P2GM0CTR P2G Memory Space 0 Control Register
P2GM1GBASE P2G Memory Space 1 G-Bus Base Address Register
P2GM1CTR P2G Memory Space 1 Control Register
P2GM2GBASE P2G Memory Space 2 G-Bus Base Address Register
P2GM2CTR P2G Memory Space 2 Control Register
P2GIOGBASE P2G I/O Space G-Bus Base Address Register
P2GIOCTR P2G IO Space Control Register
G2PCFGADRS G2P Configuration Address Register
G2PCFGDATA G2P Configuration Data Register
⎯
(Reserved)
⎯
(Reserved)
⎯
(Reserved)
G2PINTACK G2P Interrupt Acknowledge Data Register
G2PSPC G2P Special Cycle Data Register
PCICDATA0 Configuration Data 0 Register
PCICDATA1 Configuration Data 1 Register
PCICDATA2 Configuration Data 2 Register
PCICDATA3 Configuration Data 3 Register
PDMCA PDMAC Chain Address Register
PDMGA PDMAC G-Bus Address Register
PDMPA PDMAC PCI Bus Address Register
PDMCTR PDMAC Count Register
PDMCFG PDMAC Configuration Register
PDMSTATUS PDMAC Status Register
10-25
Chapter 10 PCI Controller
Register Name