Toshiba TMPR4925 Manual page 195

Bits Mnemonic Field Name
9 CHNEN Chain Enable
8 XFACT Transfer Active
⎯
7:6 Reserved
5 SMPCHN Simple Chain
4:2 XFSZ Transfer Set Size
1 MEMIO Memory to I/O
0 SNGAD Single Address
Chain Enable (Initial value: 0, R)
This bit indicates whether Chain operation is being performed. Read Only.
This bit is cleared when either the Master Enable bit (DMMCR.MSTEN) is cleared or
the Channel Reset bit (DMCCRn.CHRST) is set. This bit is set if a value other than
"0" is set when the CPU writes to the DMA Chain Address Register (DMCHARn) or
when a Chain transfer writes DMA Command Descriptor. This bit is then cleared
when "0" is set to the DMA Chain Address Register (DMCHARn).
1: If transfer completes due to the current DMA Channel Register setting, a DMA
Command Descriptor is loaded in the DMA Channel Register from the specified
DMA Chain Address Register (DMCHARn) address, then DMA transfer continues.
0: Further transfer does not start even if transfer completes due to the current DMA
Channel Register setting.
Transfer Active (Initial value: 0, R/W)
DMA transfer is performed according to the DMA Channel Register setting when this
bit is set. This bit is automatically set when a value other than "0" is set in the DMA
Chain Address Register (DMCHARn). DMA transfer is then initiated. This bit is
automatically cleared either when DMA transfer ends normally it is stopped due to an
error.
1: Perform DMA transfer.
0: Do not perform DMA transfer.
Please write "00" (Initial value: 00, R/W).
Simple Chain (Initial value: 0, R/W)
This bit selects the DMA Channel Register that loads data from DMA Command
Descriptors during Chain DMA transfer.
1: Data is only loaded to the four following DMA Channel Registers: the Chain
Address Register (DMCHARn), the Source Address Register (DMSARn), the
Destination Address Register (DMDARn), and the Count Register (DMCNTRn).
0: Data is loaded to all eight DMA Channel Registers.
Transfer Set Size (Initial value: 000, R/W)
These bits set the transfer data size of each bus operation in the internal bus.
When the transfer set size is set to four words or greater, the data size actually
transferred during a single bus operation does not always match the transfer set size.
Refer to "8.3.7.2 Burst Transfer During Single Address Transfer" and "8.3.8.2 Burst
Transfer During Dual Address Transfer" for more information.
000: 1 byte
001: 2 bytes
010: 4 bytes
011: (Reserved)
100: 4 words
101: 8 words
110: 16 words (Single Address transfer only)
111: 32 words (Single Address transfer only)
Memory to I/O (Initial value: 0, R/W)
This bit specifies the transfer direction during Single Address transfer
(DMCCRn.SNGAD = 1). Clear this bit when in the Memory Fill Transfer mode.
The setting of this bit is ignored when Dual Address transfer is set (DMCCRn.SNGAD
= 0).
1: From memory to I/O
0: From I/O to memory
Single Address (Initial value: 0, R/W)
This bit specifies whether the transfer method is Single Address transfer or Dual
Address transfer.
1: Single Address transfer
0: Dual Address transfer
Figure 8.4.2 DMA Channel Control Register (4/4)
8-27
Chapter 8 DMA Controller
Description