Registers - Toshiba TMPR4925 Manual

8.4

Registers

Reference Offset Address
8.4.6 0xB000
8.4.4 0xB004
8.4.5 0xB008
8.4.9 0xB00C
8.4.7 0xB010
8.4.8 0xB014
8.4.2 0xB018
8.4.3 0xB01C
8.4.6 0xB020
8.4.4 0xB024
8.4.5 0xB028
8.4.9 0xB02C
8.4.7 0xB030
8.4.8 0xB034
8.4.2 0xB038
8.4.3 0xB03C
8.4.6 0xB040
8.4.4 0xB044
8.4.5 0xB048
8.4.9 0xB04C
8.4.7 0xB050
8.4.8 0xB054
8.4.2 0xB058
8.4.3 0xB05C
8.4.6 0xB060
8.4.4 0xB064
8.4.5 0xB068
8.4.9 0xB06C
8.4.7 0xB070
8.4.8 0xB074
8.4.2 0xB078
8.4.3 0xB07C
8.4.10 0xB0A4
8.4.1 0xB0A8
Table 8.4.1 DMA Controller Registers
Bit Width Mnemonic
32 DMCHAR0
32 DMSAR0
32 DMDAR0
32 DMCNTR0
32 DMSAIR0
32 DMDAIR0
32 DMCCR0
32 DMCSR0
32 DMCHAR1
32 DMSAR1
32 DMDAR1
32 DMCNTR1
32 DMSAIR1
32 DMDAIR1
32 DMCCR1
32 DMCSR1
32 DMCHAR2
32 DMSAR2
32 DMDAR2
32 DMCNTR2
32 DMSAIR2
32 DMDAIR2
32 DMCCR2
32 DMCSR2
32 DMCHAR3
32 DMSAR3
32 DMDAR3
32 DMCNTR3
32 DMSAIR3
32 DMDAIR3
32 DMCCR3
32 DMCSR3
32 DMMFDR
32 DMMCR
8-21
Chapter 8 DMA Controller
Register Name
DMA Chain Address Register 0
DMA Source Address Register 0
DMA Destination Address Register 0
DMA Count Register 0
DMA Source Address Increment Register 0
DMA Destination Address Increment Register 0
DMA Channel Control Register 0
DMA Channel Status Register 0
DMA Chain Address Register 1
DMA Source Address Register 1
DMA Destination Address Register 1
DMA Count Register 1
DMA Source Address Increment Register 1
DMA Destination Address Increment Register 1
DMA Channel Control Register 1
DMA Channel Status Register 1
DMA Chain Address Register 2
DMA Source Address Register 2
DMA Destination Address Register 2
DMA Count Register 2
DMA Source Address Increment Register 2
DMA Destination Address Increment Register 2
DMA Channel Control Register 2
DMA Channel Status Register 2
DMA Chain Address Register 3
DMA Source Address Register 3
DMA Destination Address Register 3
DMA Count Register 3
DMA Source Address Increment Register 3
DMA Destination Address Increment Register 3
DMA Channel Control Register 3
DMA Channel Status Register 3
DMA Memory Fill Data Register
DMA Master Control Register